AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 16

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9510
STATUS PIN
Table 10.
Parameter
OUTPUT CHARACTERISTICS
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
POWER
Table 11.
Parameter
POWER-UP DEFAULT MODE POWER DISSIPATION
POWER DELTA
Output Voltage High (V
Output Voltage Low (V
Capacitance
Power Dissipation
Power Dissipation
Power Dissipation
Full Sleep Power-Down
Power-Down (PDB)
CLK1, CLK2 Power-Down
Divider, DIV 2 − 32 to Bypass
LVPECL Output Power-Down (PD2, PD3)
LVDS Output Power-Down
CMOS Output Power-Down (Static)
CMOS Output Power-Down (Dynamic)
CMOS Output Power-Down (Dynamic)
Delay Block Bypass
PLL Section Power-Down
OL
OH
)
)
Min
2.7
100
3
Typ
0.4
Max
Min
10
23
50
80
56
115
125
20
5
Unit
V
V
MHz
pF
Typ
550
35
60
15
27
65
92
70
150
165
24
15
Rev. A | Page 16 of 60
Test Conditions/Comments
When selected as a digital output (CMOS); there are other modes
in which the STATUS pin is not CMOS digital output. See Figure 37.
Applies when PLL mux is set to any divider or counter output,
or PFD up/down pulse. Also applies in analog lock detect mode.
Usually debug mode only. Beware that spurs may couple
to output when this pin is toggling.
On-chip capacitance; used to calculate RC time
constant for analog lock detect readback. Use a pull-up resistor.
Max
600
1.1
1.3
1.5
60
80
25
33
75
110
85
190
210
60
40
Unit
mW
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
Power-up default state; does not include power
dissipated in output load resistors. No clock.
All outputs on. Four LVPECL outputs @ 800 MHz,
4 LVDS out @ 800 MHz. Does not include power
dissipated in external resistors.
All outputs on. Four LVPECL outputs @ 800 MHz,
4 CMOS out@ 62 MHz (5 pF load). Does not include
power dissipated in external resistors.
All outputs on. Four LVPECL outputs @ 800 MHz,
4 CMOS out @ 125 MHz (5 pF load). Does not include
power dissipated in external resistors.
Maximum sleep is entered by setting 0Ah<1:0> = 01b
and 58h<4> = 1b. This powers off the PLL BG and the
distribution BG references. Does not include power
dissipated in terminations.
Set the FUNCTION pin for PDB operation by setting
58h<6:5> = 11b. Pull PDB low. Does not include
power dissipated in terminations.
For each divider.
For each output. Does not include dissipation
in termination (PD2 only).
For each output.
For each output. Static (no clock).
For each CMOS output, single-ended.
Clocking at 62 MHz with 5 pF load.
For each CMOS output, single-ended.
Clocking at 125 MHz with 5 pF load.
Versus delay block operation at 1 ns fs
with maximum delay; output clocking at 25 MHz.