MPC9773AE IDT, Integrated Device Technology Inc, MPC9773AE Datasheet

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MPC9773AE

Manufacturer Part Number
MPC9773AE
Description
IC PLL CLK GEN 1:12 3.3V 52-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of MPC9773AE

Pll
Yes with Bypass
Input
LVCMOS, LVPECL
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
3:12
Differential - Input:output
Yes/No
Frequency - Max
242.5MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Frequency-max
242.5MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
3.3 V 1:12 LVCMOS PLL Clock
Generator
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V 1:12 LVCMOS PLL Clock
Generator
for high-performance low-skew clock distribution in mid-range to high-
performance networking, computing, and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
Functional Description
MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system
baseline timing signals.
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-
figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
MPC9773. The MPC9773 has an internal power-on reset.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept
down support
52-lead Pb-free package available
1:12 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 242.5 MHz
Maximum output skew of 250 ps
Differential PECL reference clock input
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (refer to Application Section)
Supports up to three individual generated output clock frequencies
Synchronous output clock stop circuitry for each individual output for power
Drives up to 24 clock lines
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MPC973
1
PLL CLOCK GENERATOR
52-LEAD LQFP PACKAGE
52-LEAD LQFP PACKAGE
3.3 V 1:12 LVCMOS
Pb-FREE PACKAGE
MPC9773
CASE 848D-03
CASE 848D-03
FA SUFFIX
AE SUFFIX
DATA SHEET
Rev 5, 08/2005
MPC9773
MPC9773
MPC9773

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MPC9773AE Summary of contents

Page 1

Freescale Semiconductor Technical Data 3.3 V 1:12 LVCMOS PLL Clock 3.3 V 1:12 LVCMOS PLL Clock Generator Generator The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high-performance low-skew clock distribution in mid-range to high- ...

Page 2

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator All input resistors have a value PCLK 1 PCLK CCLK0 0 1 CCLK1 CCLK_SEL V CC REF_SEL FB_IN VCO_SEL PLL_EN V CC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] ...

Page 3

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Table 1. Pin Configuration Pin I/O CCLK0 Input LVCMOS CCLK1 Input LVCMOS PCLK, PCLK Input LVPECL FB_IN Input LVCMOS CCLK_SEL Input LVCMOS REF_SEL Input LVCMOS VCO_SEL Input LVCMOS PLL_EN Input LVCMOS MR/OE ...

Page 4

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Table 3. Output Divider Bank A (N VCO_SEL FSEL_A1 FSEL_A0 Table 4. Output Divider Bank B ...

Page 5

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Table 7. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch-Up Immunity C Power Dissipation Capacitance PD C Input ...

Page 6

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Table 10. AC Characteristics (V CC Symbol Characteristics f Input Reference Frequency REF Input Reference Frequency in PLL Bypass Mode f VCO Frequency Range VCO f Output Frequency MAX f Serial Interface ...

Page 7

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Table 10. AC Characteristics (V Symbol BW PLL Closed Loop Bandwidth t Maximum PLL Lock Time LOCK 1. AC characteristics apply for parallel output termination of 50 Ω The ...

Page 8

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ M ÷ ...

Page 9

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9773 allows designers, under software control, to implement power management into the clock distribution design. A ...

Page 10

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator SYNC Output Description The MPC9773 has a system synchronization pulse output QSYNC. In configurations for which the output frequency relationships are not integer multiples of each other, QSYNC provides a signal for ...

Page 11

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Power Supply Filtering The MPC9773 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise ...

Page 12

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Due to the statistical nature of I/O jitter, an RMS value (1 σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Table 12. Confidence ...

Page 13

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated ...

Page 14

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Pulse Generator Ω Differential Pulse Generator Ω MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device ...

Page 15

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 17. Output-to-Output Skew ...

Page 16

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 16 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE Advanced ...

Page 17

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE ...

Page 18

MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 18 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE 18 ...

Page 19

MC100EP111 MC88LV926 MPC9773 MPC92459 PART NUMBERS 3.3 V 1:12 LVCMOS PLL Clock Generator 900 MHz Low Voltage LVDS Clock Synthesizer Low–Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver Low Skew CMOS PLL 68060 Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate ...

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