MPC9773AE IDT, Integrated Device Technology Inc, MPC9773AE Datasheet - Page 8

• Manufacturer Part Number: MPC9773AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9773AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: Yes/No
• Frequency - Max: 242.5MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 242.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
MPC9773 Configurations
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
where f
clock source (CCLKO, CCLK1 or PCLK), M is the PLL
feedback divider and N is an output divider. The PLL
feedback divider is configured by the FSEL_FB[2:0] and the
output dividers are individually configured for each output
bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0]
inputs.
feedback-divider M is limited by the specified VCO frequency
range. f
frequency range of 200 to 480 MHz in order to achieve stable
PLL operation:
or a divide-by-two and can be used to situate the VCO into
MPC9773
8
f
f
REF
REF
Configuring the MPC9773 amounts to properly configuring
The reference frequency f
The PLL post-divider VCO_SEL is either a divide-by-one
MPC9773 example configuration (feedback of
QFB = 33.3 MHz, f
M = 12, N
= 33.3 MHz
Frequency Range
REF
REF
f
VCO,MIN
QA outputs
QB outputs
QC outputs
is the reference frequency of the selected input
Input
and M must be configured to match the VCO
Figure 3. Example Configuration
A
101
11
00
00
PLL
= 12, N
÷M
≤
1
(f
CCLK_SEL
CCLK0
CCLK1
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_FB[2:0]
REF
f
33.3 MHz (Feedback)
OUT
VCO
B
⋅
= f
VCO_SEL
= 4, N
÷VCO_SEL
MPC9773
REF
= 400 MHz, VCO_SEL = ÷1,
16.6 MHz
16.6 MHz
100 MHz
REF
50 MHz
⋅ M ÷ N
Min
C
and the selection of the
QC[3:0]
QA[3:0]
QB[3:0]
= 2).
QFB
⋅
M)
≤
÷N
f
VCO,MAX
120 MHz
240 MHz
40 MHz
40 MHz
APPLICATIONS INFORMATION
Max
33.3 MHz
100 MHz
200 MHz
f
OUT
8
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio.
the VCO frequency and output divider:
Table 11. MPC9773 Divider
dividers, and
configurations for the MPC9773.
Divider
N
N
N
The output frequency for each bank can be derived from
Table 11
M
f
REF
A
B
C
MPC9773 example configuration (feedback of
QFB = 25 MHz, f
M = 10, N
f
f
f
Frequency Range
QA[0:3]
QB[0:3]
QC[0:3]
= 25 MHz
Divider FSEL_A[0:1]
Divider FSEL_B[0:1]
Divider FSEL_C[0:1]
QC outputs
QA outputs
QB outputs
Bank A Output
Bank B Output
Bank C Output
PLL Feedback
FSEL_FB[0:3]
shows the various PLL feedback and output
Input
= f
= f
Figure 4. Example Configuration
= f
Function
Figure 3
A
011
VCO
VCO
VCO
00
00
00
= 4, N
1
CCLK0
CCLK1
CCLK_SEL
VCO_SEL
FB_IN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_FB[2:0]
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
÷ (VCO_SEL ⋅ N
VCO
25 MHz (Feedback)
and
B
Advanced Clock Drivers Device Data
= 4, N
MPC9773
= 250 MHz, VCO_SEL = ÷1,
Figure 4
VCO_SEL
100 MHz
20 MHz
50 MHz
50 MHz
Min
C
÷1
÷2
÷1
÷2
÷1
÷2
÷1
÷2
= 2).
QC[3:0]
QA[3:0]
QB[3:0]
Freescale Semiconductor
QFB
display example
A
B
C
)
)
)
8, 12, 16, 20, 24, 32, 40
4, 6, 8, 10, 12, 16
8, 12, 16, 24
8, 12, 16, 20
4, 8, 12, 16
120 MHz
120 MHz
240 MHz
4, 6, 8, 12
4, 6, 8, 10
48 MHz
2, 4, 6, 8
Values
Max
62.5 MHz
62.5 MHz
125 MHz
NETCOM
MPC9773