MPC9773AE IDT, Integrated Device Technology Inc, MPC9773AE Datasheet - Page 7

• Manufacturer Part Number: MPC9773AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9773AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: Yes/No
• Frequency - Max: 242.5MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 242.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 10. AC Characteristics (V
10. Period jitter is valid for all outputs in the same divider configuration.
11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to
12. –3 dB point of PLL transfer characteristics.
BW
t
LOCK
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: f
3. V
4. Calculation of reference duty cycle limits: DC
5. The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
6. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t
7. Excluding QSYNC output. Refer to
8. Output duty cycle is DC = (0.5 ± 200 ps ⋅ f
9. Cycle jitter is valid for all outputs in the same divider configuration.
Symbol
and the input swing lies within the V
be guaranteed if t
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
PLL Closed Loop Bandwidth
Maximum PLL Lock Time
R
, t
F
are within the specified range.
Characteristics
CC
APPLICATIONS INFORMATION
PP
= 3.3 V ± 5%, T
(AC) specification. Violation of V
(12)
OUT
REF,MIN
)
⋅
100%. E.g., the DC range at f
= t
A
÷ 10 feedback
÷ 12 feedback
÷ 16 feedback
÷ 20 feedback
÷ 24 feedback
÷ 32 feedback
÷ 40 feedback
PW,MIN
= -40°C to 85°C)
÷ 4 feedback
÷ 6 feedback
÷ 8 feedback
APPLICATIONS INFORMATION
⋅ f
REF
7
TT
⋅ 100% and DC
for part-to-part skew calculation.
.
CMR
Min
(1), (2)
or V
OUT
PP
= 100 MHz is 48% < DC < 52%. T = output period.
impacts static phase offset t
REF,MAX
1.20 – 3.50
0.70 – 2.50
0.50 – 1.80
0.45 – 1.20
0.30 – 1.00
0.25 – 0.70
0.20 – 0.55
0.17 – 0.40
0.12 – 0.30
0.11 – 0.28
(∅)
[s] = t
Typ
for I/O jitter vs. VCO frequency.
= 100% – DC
(∅)
[°] ÷ (f
Max
REF
10
REF
(∅)
= f
, t
REF,MIN
⋅ 360°).
PW,MIN
VCO
(∅)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
÷ (M ⋅ VCO_SEL).
.
.
, DC and f
Condition
MAX
CMR
MPC9773
can only
range
NETCOM
MPC9773
7