MPC9773AE IDT, Integrated Device Technology Inc, MPC9773AE Datasheet - Page 9

• Manufacturer Part Number: MPC9773AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9773AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: Yes/No
• Frequency - Max: 242.5MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 242.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
Advanced Clock Drivers Device Data
Freescale Semiconductor
MPC9773 Individual Output Disable (Clock Stop)
Circuitry
MPC9773 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC9773 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12-bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
writing logic ‘0’ to the respective stop enable bit. Likewise, the
The individual clock stop (output enable) control of the
The user can program an output clock to stop (disable) by
STOP_DATA
STOP_CLK
START
QA0
QA1
Figure 5. Clock Stop Circuit Programing
QA2
QA3
QB0
9
QB1
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would normally be in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free-running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC9773 can sample each
STOP_DATA bit with the rising edge of the free-running
STOP_CLK signal. (See
The user can write to the serial input register through the
QB2
QB3
QC1
Figure
QC2
5.)
QC3
QSYNC
MPC9773
NETCOM
MPC9773
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