MPC9773AE IDT, Integrated Device Technology Inc, MPC9773AE Datasheet - Page 3

• Manufacturer Part Number: MPC9773AE
• Description: IC PLL CLK GEN 1:12 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9773AE

• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:12
• Differential - Input:output: Yes/No
• Frequency - Max: 242.5MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 242.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
Advanced Clock Drivers Device Data
Freescale Semiconductor
Table 1. Pin Configuration
Table 2. Function Table (Configuration Controls)
CCLK0
CCLK1
PCLK, PCLK
FB_IN
CCLK_SEL
REF_SEL
VCO_SEL
PLL_EN
MR/OE
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
INV_CLK
STOP_CLK
STOP_DATA
QA[0-3]
QB[0-3]
QC[0-3]
QFB
QSYNC
GND
V
V
REF_SEL
CCLK_SEL
VCO_SEL
PLL_EN
INV_CLK
MR/OE
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency
CC_PLL
CC
Control
ratios. See
Pin
Default
1
1
1
1
1
1
Table 3
Supply
Supply
Supply
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Selects CCLKx as the PLL reference clock
Selects CCLK0
Selects VCO ÷ 2. The VCO frequency is scaled by a factor of 2 (low VCO
frequency range).
Test mode with the PLL bypassed. The reference clock is substituted for the
internal VCO output. MPC9773 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
QC2 and QC3 are in phase with QC0 and QC1
Outputs disabled (high-impedance state) and device is reset. During reset/
output disable the PLL feedback loop is open and the internal VCO is tied to
its lowest frequency. The MPC9773 requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback path is interrupted.
The length of the reset pulse should be greater than one reference clock
cycle (CCLKx). The device is reset by the internal power-on reset (POR)
circuitry during power-up.
I/O
to
Table 6
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
Ground
and the Applications Section for supported frequency ranges and output to input frequency ratios.
Type
V
V
CC
CC
PLL reference clock
Alternative PLL reference clock
Differential LVPECL reference clock
PLL feedback signal input, connect to an QFB
LVCMOS clock reference select
LVCMOS/PECL reference clock select
VCO operating frequency select
PLL enable/PLL bypass mode select
Output enable/disable (high-impedance tristate) and device reset
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
Frequency divider select for the QFB output
Clock phase selection for outputs QC2 and QC3
Clock input for clock stop circuitry
Configuration data input for clock stop circuitry
Clock outputs (Bank A)
Clock outputs (Bank B)
Clock outputs (Bank C)
PLL feedback output. Connect to FB_IN.
Synchronization pulse output
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an external RC
filter for the analog power supply pin V
Positive power supply for I/O and core. All V
supply for correct operation
0
3
CC_PLL
Function
CC
. Please refer to applications section for details.
pins must be connected to the positive power
Selects the LVPECL inputs as the PLL
reference clock
Selects CCLK1
Selects VCO ÷ 1 (high VCO frequency
range)
Normal operation mode with PLL
enabled.
QC2 and QC3 are inverted (180° phase
shift) with respect to QC0 and QC1
Outputs enabled (active)
1
MPC9773
NETCOM
MPC9773
3