ISL12020MIRZ Intersil, ISL12020MIRZ Datasheet
ISL12020MIRZ
Specifications of ISL12020MIRZ
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ISL12020MIRZ Summary of contents
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... IRQ/FOUT -40 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc Bus™ trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas Inc. 2008, 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ...
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... PART NUMBER (Note 3) MARKING ISL12020MIRZ (Note 2) ISL 12020MIRZ ISL12020MIRZ-T (Notes 1, 2) ISL 12020MIRZ 1. Please refer to TB347 for details on reel specifications. 2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (lead in high melt temp solder for internal connections) and exemption 5 (lead in piezoelectric elements) ...
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Table of Contents Block Diagram .................................................. 2 Pin Descriptions ............................................... 4 Absolute Maximum Ratings .............................. 5 Electrical Specifications .....................................6 SDA vs SCL Timing............................................ 8 Symbol Table .................................................... 8 Typical Performance Curves ............................. 8 General Description ........................................ 10 Functional Description.................................... 10 ...
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Pin Configuration Pin Descriptions PIN NUMBER SYMBOL Crystal Connection. The X1 and X2 pins are the input and output, respectively inverting 16, 17, 18, X1 amplifier and are also connected to the ...
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... Thermal Resistance (Typical) 20 Lead DFN (Notes Storage Temperature . . . . . . . . . . . . . . . -40°C to +85°C + 0.3V Pb-Free Reflow Profile (Note .see link below DD http://www.intersil.com/pbfree/Pb-FreeReflow.asp Test Conditions +2.7 to +5.5V stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. CONDITIONS (Note 10) ...
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DC Operating Characteristics - RTC SYMBOL PARAMETER IRQ/F (OPEN DRAIN OUTPUT) OUT V Output Low Voltage OL Power-Down Timing Test Conditions: V Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER V V Negative Slew rate ...
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I2C Interface Specifications SYMBOL PARAMETER t START Condition Hold Time HD:STA t Input Data Setup Time SU:DAT t Input Data Hold Time HD:DAT t STOP Condition Setup Time SU:STO t STOP Condition Hold Time HD:STO t Output Data Hold Time ...
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SDA vs SCL Timing t F SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V 5.0V 1533Ω SDA AND IRQ/F OUT 100pF FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE ...
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Typical Performance Curves 5.5V BAT 3. -40 - TEMPERATURE (°C) FIGURE TEMPERATURE DD1 5. ...
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... Functional Description Power Control Operation The power control circuit accepts a V input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12020M for years. ...
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BATTERY-BACKUP MODE TRIP V BAT BAT BATHYS FIGURE 12. BATTERY SWITCHOVER WHEN V < V BAT TRIP BATTERY-BACKUP MODE BAT V TRIP V TRIP FIGURE 13. BATTERY SWITCHOVER WHEN V > ...
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The pulsed Interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as ...
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TABLE 1. REGISTER MEMORY MAP (X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE CHANGED BY THE USER) REG ADDR. SECTION NAME 7 00h SC 0 01h MN 0 02h HR MIL RTC 03h ...
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TABLE 1. REGISTER MEMORY MAP (Continued)(X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE CHANGED BY THE USER) (Continued) REG ADDR. SECTION NAME 7 20h DstMoFd DSTE 21h DstDwFd D 22h DstDtFd D 23h ...
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OSCILLATOR FAIL BIT (OSCF) Oscillator Fail Bit indicates that the oscillator has stopped. DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ) DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the daylight saving time forward adjustment has happened DST ...
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Interrupt Control Register (INT) TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 AUTOMATIC RESET BIT (ARST) This bit enables/disables the automatic reset of the ALM, LVDD, LBAT85, and ...
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Battery Voltage Trip Voltage Register (PWR_VBAT) This register controls the trip points for the two V alarms, with levels set to approximately 85% and 75% of the nominal battery level. TABLE 7. ADDR 0Ah D RESEALB ...
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AGING AND INITIAL ANALOG TRIMMING BITS (IATR0<5:0>) The Initial Analog Trimming Register allows +32ppm to -31ppm adjustment in 1ppm/bit increments. This enables fine frequency adjustment for trimming initial crystal accuracy error or to correct for aging drift. The ISL12020M has ...
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TABLE 12. IATRO TRIMMING RANGE (Continued) IATR05 IATR04 ...
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FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT (BTSR) This bit controls the frequency of Temp Sensing and Correction. BTSR = 0 default mode is every 10 minutes, BTSR = 1 is every 1.0 minute. Note that BTSE has to be ...
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TABLE 17. FINAL ANALOG TRIMMING REGISTER ADDR 0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0 Final Digital Trimming Register (FDTR) This register shows the final setting of DT after temperature correction read-only; ...
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After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30 a.m. on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register to “1” and ...
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Bits contain the Week of the Month information that sets the week that DST starts. The range is from and Week 7 is used to indicate the last week of the month. The ...
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DST Day/Week Reverse DstDwRv contains both the Day of the Week and the Week of the Month data for DST Reverse control. DST can be controlled either by actual date or by setting both the Week of the month and ...
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TABLE 24. XT0 VALUES XT<4:0> 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 ALPHA Hot Register ...
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SCL SDA START FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM ...
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Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device ...
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V = 2.7V ISL12020M J DD BAT TO 5.5V VDD VBAT C IN 0.1µF GND FIGURE 20. SUGGESTED BATTERY-BACKUP CIRCUIT The diode, D will add a small drop to the battery BAT voltage but will protect the circuit should ...
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Temperature Compensation Operation The ISL12020M temperature compensation feature needs to be enabled by the user. This must be done in a specific order as follows. 1. Read register 0Dh, the BETA register. This register contains the 5-bit BETA trimmed value, ...
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... Changed "Pb-Free" on page 1 and page 3 under package to: "RoHS Compliant" 10/22/09 FN6667.4 Converted to New Intersil Template - Matched front page to match ISL12022M with the exception of pinout change from SOIC to DFN. Updated ordering information by numbering all notes, setting up links, added MSL (Moisture Sensitivity Level) note. Updated word "Pinout" to " ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...
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Package Outline Drawing L20.5.5x4.0 20 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 07/09 5.5 PIN 1 TOP VIEW INDEX AREA (4.95) (2X 0.20) (4.50 ) 10X 0.50 10X 0.50 10X 0. 0.25 PACKAGE BOUNDARY 2X 1.50 0.68 ...