ISL12020MIRZ Intersil, ISL12020MIRZ Datasheet - Page 26

• Manufacturer Part Number: ISL12020MIRZ
• Description: IC RTC/CALENDAR TEMP SNSR 20-DFN
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12020MIRZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
All I
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The ISL12020M continuously
monitors the SDA and SCL lines for the START condition
and does not respond to any command until this
condition is met (see Figure 15). A START condition is
ignored during the power-up sequence.
All I
STOP condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH (see Figure 15). A STOP condition
at the end of a read operation or at the end of a write
operation to memory only places the device in its
standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting
device, either master or slave, releases the SDA bus
after transmitting eight bits. During the ninth clock cycle,
the receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 16).
2
2
C interface operations must begin with a START
C interface operations must be terminated by a
SDA OUTPUT FROM
FROM RECEIVER
TRANSMITTER
SDA OUTPUT
SCL FROM
SDA
MASTER
SCL
SIGNAL AT SDA
THE ISL12020M
SIGNALS FROM
SIGNALS FROM
FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
THE MASTER
FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS
26
START
START
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
A
R
S
T
T
1
IDENTIFICATION
1
1
0
1
BYTE
STABLE
1 1 1
ISL12020M
DATA
0
A
K
C
CHANGE
WRITE
DATA
0 0 0 0
The ISL12020M responds with an ACK after recognition
of a START condition followed by a valid Identification
Byte, and once again, after successful receipt of an
Address Byte. The ISL12020M also responds with an ACK
after receiving a Data Byte of a write operation. The
master must respond with an ACK after receiving a Data
Byte of a read operation.
Device Addressing
Following a start condition, the master must output a
Slave Address Byte. The 7 MSBs are the device
identifiers. These bits are “1101111” for the RTC
registers and “1010111” for the User SRAM.
The last bit of the Slave Address Byte defines a read or
write operation to be performed. When this R/W bit is a
“1”, a read operation is selected. A “0” selects a write
operation (refer to Figure 18).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12020M compares the device identifier and
ADDRESS
BYTE
STABLE
DATA
8
A
C
K
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
O
S
T
P
February 11, 2010
FN6667.4