ISL12020MIRZ Intersil, ISL12020MIRZ Datasheet - Page 27

• Manufacturer Part Number: ISL12020MIRZ
• Description: IC RTC/CALENDAR TEMP SNSR 20-DFN
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12020MIRZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

device select bits with “1101111” or “1010111”. Upon a
correct compare, the device outputs an acknowledge on
the SDA line.
Following the Slave Byte is a one byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up, the
internal address counter is set to address 00h, so a
current address read starts at address 00h. When
required, as part of a random read, the master must
supply the 1 Word Address Bytes, as shown in Figure 19.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. For a random read of the Control/Status
Registers, the slave byte must be “1101111x” in both
places.
FIGURE 18. SLAVE ADDRESS, WORD ADDRESS, AND
Write Operation
A Write operation requires a START condition, followed by
a valid Identification Byte, a valid Address Byte, a Data
Byte, and a STOP condition. After each of the three
bytes, the ISL12020M responds with an ACK. At this
time, the I
Read Operation
A Read operation consists of a three byte instruction,
followed by one or more Data Bytes (see Figure 19).
The master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit set to “0”, an Address Byte, a second START, and a
second Identification byte with the R/W bit set to “1”.
After each of the three bytes, the ISL12020M responds
with an ACK. Then the ISL12020M transmits Data Bytes
as long as the master responds with an ACK during the
SCL cycle following the eighth bit of each byte. The
master terminates the read operation (issuing a STOP
A7
D7
1
FROM THE
SIGNALS FROM
SIGNALS
MASTER
SIGNAL AT
A6
D6
1
THE SLAVE
2
SDA
C interface enters a standby state.
A5
D5
0
DATA BYTES
S
T
A
R
T
A4
D4
1
1
IDENTIFICATION
1
D3
A3
BYTE WITH
1
0
R/W = 0
1 1 1 1
27
1
D2
A2
FIGURE 19. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
0
1
D1
A1
A
K
C
R/
A0
D0
ADDRESS
BYTE
SLAVE
ADDRESS BYTE
WORD
ADDRESS
DATA BYTE
ISL12020M
A
C
K
S
T
A
R
T
IDENTIFICATION
1
1
BYTE WITH
R/W = 1
0
condition) following the last bit of the last Data Byte
(see Figure 19).
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer’s initial value is
determined by the Address Byte in the Read operation
instruction, and increments by one during transmission
of each Data Byte. After reaching the memory location
2Fh, the pointer “rolls over” to 00h, and the device
continues to output data for each ACK received.
Application Section
Battery-Backup Details
The ISL12020M has automatic switchover to
battery-backup when the V
mode threshold. A wide variety of backup sources can be
used, including standard and rechargeable lithium, Super
Capacitors, or regulated secondary sources. The serial
interface is disabled in battery-backup, while the
oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents
as well.
The input voltage range for VBAT is 1.8V to 5.5V, but
keep in mind the temperature compensation only
operates for V
guaranteed to operate with a V
should be changed before discharging to that level. It is
strongly advised to monitor the low battery indicators in
the status registers and take action to replace discharged
batteries.
If a Super Capacitor is used, it is possible that it may
discharge to below 1.8V during prolonged power-down.
Once powered up, the device may lose serial bus
communications until both V
down together. To avoid that situation, including
situations where a battery may discharge deeply, the
circuit in Figure 20 can be used.
1 1 1 1
1
A
K
C
FIRST READ
BAT
DATA BYTE
> 2.7V. Note that the device is not
A
C
K
DD
DD
drops below the VBAT
BAT
and V
A
C
K
< 1.8V, so the battery
LAST READ
DATA BYTE
BAT
are powered
February 11, 2010
FN6667.4
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