LTC2498IUHF#PBF Linear Technology, LTC2498IUHF#PBF Datasheet - Page 18

• Manufacturer Part Number: LTC2498IUHF#PBF
• Description: IC ADC 24BIT 16CH 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2498IUHF#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 480µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 0.008KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±2.75V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Integral Nonlinearity Error: 10ppm of Vref
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 38
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applications inForMation
LTC2498
INPUT DATA FORMAT
The LTC2498 serial input word is 13 bits long and contains
two distinct sets of data. The first set (SGL, ODD, A2, A1,
A0) is used to select the input channel. The second set
of data (IM, FA, FB, SPD) is used to select the frequency
rejection, speed mode (1x, 2x), and temperature mea-
surement.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0 – CH1 (IN
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
a new word may be written into the device.
The first 3 bits shifted into the device consist of two preen-
able bits and one enable bit. As demonstrated in Figure 3,
the first three bits shifted into the device enable the device
configuration and input channel selection. Valid settings for
these three bits are 000, 100 and 101. Other combinations
should be avoided. If the first three bits are 000 or 100, the
following data is ignored (don’t care) and the previously
selected input channel and configuration remain valid for
the next conversion.
If the first 3 bits shifted into the device are 101, then the
next 5 bits select the input channel for the next conversion
cycle, see Table 3.

Table 2. Output Data Format
Differential Input Voltage
V
V
0.5 • V
0.25 • V
0.25 • V
0
–1LSB
–0.25 • V
–0.25 • V
–0.5 • V
V
*The differential input voltage V
***The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
IN
IN
IN
*
* ≥ 0.5 • V
* < –0.5 • V
REF
REF
REF
REF
REF
REF
** – 1LSB
**
** – 1LSB
**
**
** – 1LSB
REF
REF
**
**
IN
= IN+ – IN–. **The differential reference voltage V
Bit 31
EOC
0
0
0
0
0
0
0
0
0
0
+
= CH0, IN
Bit 30
DMY
0
0
0
0
0
0
0
0
0
0
–
1/0***
Bit 29
=
SIG
1
1
1
1
0
0
0
0
0
The first input bit following the 101 sequence (SGL)
determines if the input selection is differential (SGL = 0)
or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of 16 channels is selected as the positive
input. The negative input is COM for all single ended opera-
tions. The remaining 4 bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
configuration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter configuration. This is useful in systems using
the same rejection/speed for all input channels and for
backward compatibility with the LTC2418/LTC2414 families
of delta sigma ADCs.
A new configuration can be loaded into the device by
setting EN2 = 1, see Table 4. The first bit (IM) is used
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next 2 bits (FA and FB) are used to set the rejection
frequency. The final bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the final conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates
Bit 28
MSB
1
0
0
0
0
1
1
1
1
0
REF
= REF+ – REF–.
Bit 27
0
1
1
0
0
1
1
0
0
1
Bit 26
0
1
0
1
0
1
0
1
0
1
Bit 25
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
…
Bit 0
0
1
0
1
0
1
0
1
0
1
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