LTC2498IUHF#PBF Linear Technology, LTC2498IUHF#PBF Datasheet - Page 23

• Manufacturer Part Number: LTC2498IUHF#PBF
• Description: IC ADC 24BIT 16CH 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC2498IUHF#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 480µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 0.008KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±2.75V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Integral Nonlinearity Error: 10ppm of Vref
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 38
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applications inForMation
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 32nd falling edge of SCK, see Figure 7. On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle. If CS goes HIGH between the 8th
falling edge and the 16th falling edge of SCK, the new
channel is still loaded, but the converter configuration
remains unchanged. In order to program both the input
channel and converter configuration, CS must go HIGH
after the 16th falling edge of SCK (at this point all data
has been shifted into the device).
(EXTERNAL)
SDO
SCK
SDI
CS
CONVERSION
Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
DON'T CARE
SLEEP
BIT 31
10µF
1
EOC
2.7V TO 5.5V
1
BIT 30
“0”
0
2
0.1V TO V
REFERENCE
0.1µF
ANALOG
INPUTS
VOLTAGE
BIT 29
SIG
EN
3
CC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24
MSB
•
•
•
•
•
•
SGL
28
29
30
15
16
23
4
8
7
V
REF
REF
CH0
CH7
CH8
CH15
COM
DATA INPUT/OUTPUT
CC
•
•
•
•
•
•
ODD
LTC2498
+
–
5
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal, see Figure 8. CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after V
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
GND
SDO
SCK
SDI
CS
A2
f
6
O
1,3,4,5,6,31,32,33,39
38
34
35
37
36
A1
7
4-WIRE
SPI INTERFACE
A0
8
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
BIT 23
CC
exceeds 2V. The level applied to
CONVERSION
DON'T CARE
Hi-Z
LTC2498
SLEEP
2498 F07

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