AD7266BCP Analog Devices Inc, AD7266BCP Datasheet - Page 24

• Manufacturer Part Number: AD7266BCP
• Description: IC ADC 12BIT 3CHAN 2MSPS 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7266BCP

• Design Resources: AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039)
• Number Of Bits: 12
• Sampling Rate (per Second): 2M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 33.6mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• For Use With: EVAL-AD7266CBZ - BOARD EVALUATION FOR AD7266
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7266
AD7266 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interface directly to the
AD7266 without any glue logic required. The availability of
secondary receive registers on the serial ports of the Blackfin®
DSPs means only one serial port is necessary to read from both
D
D
ADSP-BF53x. The SPORT0 Receive Configuration 1 register
and SPORT0 Receive Configuration 2 register should be set up
as outlined in Table 9 and Table 10.
Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
Table 10. The SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)
Setting
RXSE = 1
SLEN = 1111
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
AD7266 is available to download at www.analog.com.
OUT
OUT
1
ADDITIONAL PINS OMITTED FOR CLARITY.
B of the AD7266 connected to Serial Port 0 of the
pins simultaneously. Figure 44 shows both D
AD7266
Figure 44. Interfacing the AD7266 to the ADSP-BF53x
V
D
D
1
SCLK
DRIVE
OUT
OUT
CS
A
B
Description
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
Receive MSB first
Zero fill
Internal receive clock
Receive enabled
16-bit data-word (or may be set to 1101
for 14-bit data-word)
Description
Secondary side enabled
16-bit data-word ( or may be set to 1101
for 14-bit data-word)
(SECONDARY)
(PRIMARY)
DEVICE B
DEVICE A
SERIAL
SERIAL
DR0PRI
RCLK0
RFS0
DR0SEC
SPORT0
ADSP-BF53x
V
DD
OUT
A and
1
Rev. A | Page 24 of 28
AD7266 TO TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7266. The CS input allows easy interfacing between the
TMS320C541 and the AD7266 without any glue logic required.
The serial ports of the TMS320C541 are set up to operate in
burst mode with internal CLKX0 (TX serial clock on Serial
Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial
port control registers (SPC) must have the following setup.
Table 11. Serial Port Control Register Set Up
SPC
SPC0
SPC1
The format bit, FO, may be set to 1 to set the word length to
8 bits to implement the power-down modes on the AD7266.
The connection diagram is shown in Figure 45. It is imperative
that for signal processing applications, the frame synchroniza-
tion signal from the TMS320C541 provides equidistant sampling.
The V
that of the TMS320C541. This allows the ADC to operate at a
higher voltage than its serial interface and therefore, the
TMS320C541, if necessary.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DRIVE
AD7266
Figure 45. Interfacing the AD7266 to the TMS320C541
pin of the AD7266 takes the same supply voltage as
FO
0
0
D
V
D
1
SCLK
DRIVE
OUT
OUT
CS
A
B
FSM
1
1
MCM
1
0
CLKX0
CLKR0
CLKX1
CLKR1
DR0
DR1
FSX0
FSR0
FSR1
TMS320C541
V
DD
TXM
1
0
1