CY7C1315KV18-250BZXC Cypress Semiconductor Corp, CY7C1315KV18-250BZXC Datasheet - Page 12

• Manufacturer Part Number: CY7C1315KV18-250BZXC
• Description: CY7C1315KV18-250BZXC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1315KV18-250BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Write Cycle Descriptions
The write cycle description table for CY7C1311KV18 and CY7C1313KV18 are as follows.
Write Cycle Descriptions
The write cycle description table for CY7C1911KV18 is as follows.
Notes
Document Number: 001-58904 Rev. *C
10. X = ‘Don't Care’, H = Logic HIGH, L = Logic LOW,
11. Is based on a write cycle that was initiated in accordance with the
BWS
NWS
BWS
H
H
H
H
different portions of a write cycle, as long as the setup and hold requirements are achieved.
L
L
L
L
H
H
L
L
0
0
0
/
BWS
NWS
L–H
L–H
H
H
H
H
L
L
L
L
K
–
–
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
L–H
L–H
K
–
–
L–H During the data portion of a write sequence
L–H During the data portion of a write sequence
L–H During the data portion of a write sequence
L–H No data is written into the devices during this portion of a write operation.
K
–
–
–
–
During the data portion of a write sequence, the single byte (D
During the data portion of a write sequence, the single byte (D
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
During the data portion of a write sequence
CY7C1311KV18 both nibbles (D
CY7C1313KV18 both bytes (D
CY7C1311KV18 both nibbles (D
CY7C1313KV18 both bytes (D
During the data portion of a write sequence
CY7C1311KV18 only the lower nibble (D
CY7C1313KV18 only the lower byte (D
CY7C1311KV18 only the lower nibble (D
CY7C1313KV18 only the lower byte (D
During the data portion of a write sequence
CY7C1311KV18 only the upper nibble (D
CY7C1313KV18 only the upper byte (D
CY7C1311KV18 only the upper nibble (D
CY7C1313KV18 only the upper byte (D
No data is written into the devices during this portion of a write operation.

represents rising edge.
Write Cycle Descriptions
[17:0]
[17:0]
[7:0]
[7:0]
[10, 11]
) are written into the device.
) are written into the device.
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
[3:0]
[3:0]
[7:4]
[7:4]
table. NWS
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
CY7C1313KV18, CY7C1315KV18
) is written into the device, D
) is written into the device, D
CY7C1311KV18, CY7C1911KV18
) is written into the device, D
) is written into the device, D
0
, NWS
[10, 11]
1
[8:0]
[8:0]
, BWS
) is written into the device.
) is written into the device.
0
, BWS
1
, BWS
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
2
, and BWS
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
3
can be altered on
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