CY7C1315KV18-250BZXC Cypress Semiconductor Corp, CY7C1315KV18-250BZXC Datasheet - Page 27

• Manufacturer Part Number: CY7C1315KV18-250BZXC
• Description: CY7C1315KV18-250BZXC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1315KV18-250BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-58904 Rev. *C
Parameter
Output Times
t
t
t
t
t
t
t
t
t
t
PLL Timing
t
t
t
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
32. These parameters are extrapolated from the input timing parameters (t
33. t
34. At any voltage and temperature t
35. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock) of 20 µs (min. spec.) and will
Cypress
design and are not tested in production.
lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
C/C Clock Rise (or K/K in Single
Clock mode) to Data Valid
Data Output Hold after Output C/C
Clock Rise (Active To Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock
Rise
Echo Clock High To Data Valid
Echo Clock High To Data Invalid
OutPut Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (C/C) Rise to High Z
(Active to High Z)
Clock (C/C) Rise to Low Z
Clock Phase Jitter
PLL Lock Time (K, C)
K Static to PLL Reset
[29, 30]
CHZ
is less than t
Description
(continued)
CLZ
[33, 34]
and t
[35]
CHZ
[32]
[33, 34]
less than t
[32]
AC Test Loads and
CYC
CO
/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
–0.45
–0.45
–0.25
–0.45
1.25
1.25
Min Max Min Max Min Max Min Max Min Max
.
333 MHz
20
30
–
–
–
–
–
0.45
0.45
0.25
0.45
0.20
–
–
–
–
–
–
–
–
Waveforms. Transition is measured ± 100 mV from steady-state voltage.
–0.45
–0.45
–0.27
–0.45
1.4
1.4
300 MHz
20
30
–
–
–
–
–
CY7C1313KV18, CY7C1315KV18
CY7C1311KV18, CY7C1911KV18
0.45
0.45
0.27
0.45
0.20
–
–
–
–
–
–
–
–
–0.45
–0.45
–0.30
–0.45
1.75
1.75
250 MHz
20
30
–
–
–
–
–
0.45
0.45
0.30
0.45
0.20
–
–
–
–
–
–
–
–
–0.45
–0.45
–0.35
–0.45
2.25
2.25
200 MHz
20
30
–
–
–
–
–
0.45
0.45
0.35
0.45
0.20
–
–
–
–
–
–
–
–
–0.50
–0.50
–0.40
–0.50
2.75
2.75
167 MHz
20
30
–
–
–
–
–
Page 27 of 33
0.50
0.50
0.40
0.50
0.20
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
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