CY7C1315KV18-250BZXC Cypress Semiconductor Corp, CY7C1315KV18-250BZXC Datasheet - Page 26

• Manufacturer Part Number: CY7C1315KV18-250BZXC
• Description: CY7C1315KV18-250BZXC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1315KV18-250BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document Number: 001-58904 Rev. *C
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Notes
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
31. This part has a voltage regulator internally; t
Cypress
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I
and outputs data with the output timings of that frequency range.
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
Parameter
V
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C
to C Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to K Clock Rise
(RPS, WPS)
Double data rate control setup to
Clock (K/K) Rise
(BWS
D
Address Hold after K Clock Rise
Control Hold after K Clock Rise
(RPS, WPS)
Double data rate control Hold after
Clock (K/K) Rise
(BWS
D
[29, 30]
DD
[X:0]
[X:0]
(typical) to the First Access
0
0
Hold after Clock (K/K) Rise
Setup to Clock (K/K) Rise
, BWS
, BWS
Description
POWER
1
1
, BWS
, BWS
is the time that the power must be supplied above V
2
2
, BWS
, BWS
3
3
)
)
OL
[31]
/I
OH
1.20
1.20
1.35
and load capacitance shown in (a) of
Min Max Min Max Min Max Min Max Min Max
3.0
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
333 MHz
1
0
1.30
8.4
–
–
–
–
–
–
–
–
–
–
–
–
1.32
1.32
1.49
3.3
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
300 MHz
1
0
CY7C1313KV18, CY7C1315KV18
CY7C1311KV18, CY7C1911KV18
1.45
8.4
–
–
–
–
–
–
–
–
–
–
–
–
DD
minimum initially before a read or write operation is initiated.
0.35
0.35
0.35
0.35
4.0
1.6
1.6
1.8
0.5
0.5
0.5
0.5
250 MHz
1
0
Figure
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
–
4.
5.0
2.0
2.0
2.2
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
200 MHz
1
0
8.4
2.2
–
–
–
–
–
–
–
–
–
–
–
–
6.0
2.4
2.4
2.7
0.7
0.7
0.5
0.5
0.7
0.7
0.5
0.5
167 MHz
1
0
Page 26 of 33
DDQ
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
–
= 1.5 V, input
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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