CY7C1315KV18-250BZXC Cypress Semiconductor Corp, CY7C1315KV18-250BZXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1315KV18-250BZXC
• Description: CY7C1315KV18-250BZXC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1315KV18-250BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-58904 Rev. *C
Pin Name
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC /36M
NC /72M
NC /144M
NC /288M
V
V
V
V
REF
DD
SS
DDQ
Power supply Power Supply Inputs to the Core of the Device.
Power supply Power Supply Inputs for the Outputs of the Device.
Echo clock
reference
Ground
Output
Input-
Input
Input
Input
Input
Input
N/A
N/A
N/A
N/A
N/A
I/O
(continued)
CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL Turn Off  Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull up through a 10 K or less pull up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the Device.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Switching Characteristics on page
Pin Description
CY7C1313KV18, CY7C1315KV18
CY7C1311KV18, CY7C1911KV18
26.
DDQ
, which enables the
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