PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 346

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K90 FAMILY
TABLE 21-4:
DS39957B-page 346
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSP1MSK
SSP1CON1
SSP1CON2
SSP1STAT
SSP2BUF
SSP2ADD
SSP2MSK
SSP2CON1
SSP2CON2
SSP2STAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
2:
(1)
(1)
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
Slave operating modes in 7-Bit Masking mode. See Section 21.4.3.4 “7-Bit Address Masking Mode” for
more details.
Alternate bit definitions for use in I
GIE/GIEH PEIE/GIEL
TMR5GIE
TMR5GIP
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP1 Baud Rate Reload Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
MSSP2 Baud Rate Reload Register (I
TMR5GIF
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISD7
WCOL
WCOL
GCEN
GCEN
GCEN
GCEN
MSK7
MSK7
Bit 7
SMP
SMP
—
—
—
REGISTERS ASSOCIATED WITH I
ACKSTAT
ACKSTAT ADMSK5
ACKSTAT
ACKSTAT ADMSK5
TRISC6
TRISD6
SSPOV
SSPOV
LCDIE
LCDIP
LCDIF
MSK6
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
CKE
—
—
—
TMR0IE
TRISC5
TRISD5
SSP2IF
SSP2IE
SSP2IP
SSPEN
ACKDT
SSPEN
ACKDT
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
MSK5
MSK5
Bit 5
D/A
D/A
2
2
C™ Slave mode),
C Slave mode),
2
(2)
(2)
C Slave mode operations only.
ADMSK4
ADMSK4
BLC2IE
BLC2IP
TRISC4
TRISD4
Preliminary
BLC2IF
ACKEN
ACKEN
INT0IE
TX1IE
TX1IP
TX2IE
TX2IP
TX1IF
TX2IF
MSK4
MSK4
2
2
Bit 4
CKP
CKP
C Master mode)
C Master mode)
P
P
(2)
(2)
2
C™ OPERATION
ADMSK3
ADMSK3
CTMUIF
CTMUIE
CTMUIP
SSP1IF
SSP1IE
SSP1IP
BCL1IE
BCL1IP
TRISC3
TRISD3
BCL1IF
SSPM3
SSPM3
RCEN
RCEN
MSK3
MSK3
RBIE
Bit 3
S
S
(2)
(2)
ADMSK2
ADMSK2
TMR1GIF
TMR1GIE
TMR1GIP
TMR0IF
CCP2IE
CCP2IP
HLVDIF
HLVDIE
HLVDIP
CCP2IF
TRISC2
TRISD2
SSPM2
SSPM2
MSK2
MSK2
Bit 2
PEN
R/W
PEN
R/W
(2)
(2)
ADMSK1
ADMSK1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP1IF
CCP1IE
CCP1IP
TRISC1
TRISD1
 2010 Microchip Technology Inc.
SSPM1
SSPM1
INT0IF
RSEN
RSEN
MSK1
MSK1
Bit 1
UA
UA
(2)
(2)
2
C™ mode.
TMR3GIF
TMR3GIE
TMR3GIP
RTCCIE
RTCCIP
TMR1IF
TMR1IE
TMR1IP
RTCCIF
TRISC0
TRISD0
SSPM0
SSPM0
MSK0
MSK0
RBIF
Bit 0
SEN
SEN
SEN
SEN
BF
BF
on Page:
Values
2
Reset
C™
73
75
75
75
75
75
75
75
75
75
76
76
74
74
74
74
74
80
80
80
81
80
—
—