EVAL-AD7934CB Analog Devices Inc, EVAL-AD7934CB Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7934CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7934CB

• Lead Free Status / Rohs Status: Not Compliant

CIRCUIT INFORMATION
The AD7933/AD7934 are fast, 4-channel, 10-bit and 12-bit,
single-supply, successive approximation analog-to-digital
converters. The parts operate from a 2.7 V to 5.25 V power
supply and feature throughput rates up to 1.5 MSPS.
The AD7933/AD7934 provide the user with an on-chip
track-and-hold, an internal accurate reference, an analog-to-
digital converter, and a parallel interface housed in a 28-lead
TSSOP package.
The AD7933/AD7934 have four analog input channels that
can be configured to be four single-ended inputs, two fully
differential pairs, or two pseudo differential pairs. There is
an on-chip channel sequencer that allows the user to select a
consecutive sequence of channels through which the ADC can
cycle with each falling edge of CONVST .
The analog input range for the AD7933/AD7934 is 0 V to V
or 0 V to 2 × V
the control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7933/AD7934 provide flexible power management
options to allow users to achieve the best power performance
for a given throughput rate. These options are selected by
programming PM1 and PM0, the power management bits, in
the control register.
CONVERTER OPERATION
The AD7933/AD7934 are successive approximation ADCs
based around two capacitive digital-to-analog converters (DACs).
Figure 14 and Figure 15 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. Both
figures show the operation of the ADC in differential/pseudo
differential modes. Single-ended mode operation is similar but
V
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
IN−
V
V
IN–
IN+
is internally tied to AGND. In acquisition phase, SW3 is
B
A
A
B
V
REF
REF
SW1
SW2
, depending on the status of the RANGE bit in
Figure 14. ADC Acquisition Phase
C
C
S
S
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC
REF
Rev. B | Page 17 of 32
When the ADC starts a conversion (see Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the V
otherwise, the two inputs have different settling times, resulting
in errors.
ADC TRANSFER FUNCTION
The output coding for the AD7933/AD7934 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code transitions
occur at successive LSB values (1 LSB, 2 LSBs, and so on), and
the LSB size is V
AD7934. The ideal transfer characteristics of the AD7933/AD7934
for both straight binary and twos complement output coding are
shown in Figure 16 and Figure 17, respectively.
V
V
IN+
IN–
111...111
111...110
111...000
011...111
000...010
000...001
000...000
Figure 16. AD7933/AD7934 Ideal Transfer Characteristic
B
A
A
B
V
0V
NOTES
1. V
REF
SW1
SW2
REF
REF
with Straight Binary Output Coding
Figure 15. ADC Conversion Phase
1 LSB
/1024 for the AD7933 and V
C
C
IS EITHER V
S
S
ANALOG INPUT
IN+
SW3
REF
and the V
1 LSB = V
1 LSB = V
OR 2 × V
COMPARATOR
AD7933/AD7934
REF
REF
REF
IN−
/4096 (AD7934)
/1024 (AD7933)
.
pins must match;
+V
REF
REF
CAPACITIVE
CAPACITIVE
– 1 LSB
CONTROL
/4096 for the
LOGIC
DAC
DAC