EVAL-AD7934CB Analog Devices Inc, EVAL-AD7934CB Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD7934CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7934CB

• Lead Free Status / Rohs Status: Not Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3 to 10
11
12
13
14 to
16
17
18
19
Mnemonic
V
W/B
DB0 to DB7
V
DGND
DB8/HBEN
DB9 to
DB11
BUSY
CLKIN
CONVST
DD
DRIVE
Description
Power Supply Input. The V
with a 0.1 μF capacitor and a 10 μF tantalum capacitor.
Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and from
the AD7933/AD7934 in 10-bit words on Pin DB2 to Pin DB11, or in 12-bit words on Pin DB0 to Pin DB11. When W/B
is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin
DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, tie off unused data lines to
DGND.
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow
programming of the control register. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the V
DB1) are always 0, and the LSB of the conversion result is available on DB2.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7933/AD7934 operates. Decouple this pin to DGND. The voltage at this pin may be different to that at V
should never exceed V
Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. Connect this pin
to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of
data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to, or read from, the AD7933/AD7934 are on DB0 to DB3. When reading from the device, DB4
and DB5 contain the ID of the channel to which the conversion result corresponds (see the channel address bits in
Table 10). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must be all 0s.
Note that when reading from the AD7933, the two LSBs in the low byte are 0s, and the remaining six bits are
conversion data.
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low
voltage levels for these pins are determined by the V
Busy Output. This is the logic output indicating the status of the conversion. The BUSY output goes high following
the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode
just prior to the falling edge of BUSY, on the 13
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7933/AD7934 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST initiates a conversion. The track-and-hold goes from track to
hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following power-
down, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to power up
the device.
DD
DB8/HBEN
by more than 0.3 V.
DD
V
DGND
DRIVE
range for the AD7933/AD7934 is from 2.7 V to 5.25 V. Decouple the supply to AGND
W/B
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB9
V
DD
Figure 2. Pin Configuration
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Rev. B | Page 9 of 32
(Not to Scale)
AD7933/
AD7934
TOP VIEW
2
. The frequency of the master clock input therefore determines the
DRIVE
th
rising edge of CLKIN (see Figure 34).
input. When reading from the AD7933, the two LSBs (DB0 and
28
26
25
24
23
22
21
19
18
17
16
15
27
20
DRIVE
V
V
V
V
V
AGND
CS
RD
WR
CONVST
CLKIN
BUSY
DB11
DB10
IN
IN
IN
IN
REFIN
3
2
1
0
input.
/V
REFOUT
AD7933/AD7934
DD
but