EVAL-AD7934CB Analog Devices Inc, EVAL-AD7934CB Datasheet - Page 28

• Manufacturer Part Number: EVAL-AD7934CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7934CB

• Lead Free Status / Rohs Status: Not Compliant

AD7933/AD7934
AD7933/AD7934 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7933/AD7934
and the
example of one of three DMA handshake modes. The MS
control line is actually three memory select lines. Internal
ADDR
asserted as chip selects. The DMAR
in this setup as the interrupt to signal the end of the conversion.
The rest of the interface is standard handshaking operation.
AD7933/AD7934 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 43. Select the memory-mapped address for the
AD7933/AD7934 to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7933/AD7934 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the
RD and the WR lines when interfacing to the TMS320C25, no
wait states are necessary. However, if slower logic is used, data
accesses may be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide
for details).
Data is read from the ADC using the following instruction:
where:
D is the data memory address.
ADC is the AD7933/AD7934 address.
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDR
ADSP-21065L*
IN D, ADC
0
25 to 24
TO ADDR
D0 TO D31
ADSP-21065L
DMAR
are decoded into MS
MS
WR
RD
23
Figure 42. Interfacing to the ADSP-21065L
X
1
ADDRESS BUS
DECODER
ADDRESS
ADDRESS
DATA BUS
SHARC® processor. This interface is an
LATCH
ADDRESS BUS
3 to 0
1
, these lines are then
(DMA Request 1) is used
DSP/USER SYSTEM
CS
BUSY
RD
WR
DB0 TO DB11
AD7933/
AD7934*
CONVST
X
Rev. B | Page 28 of 32
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7933/AD7934 to 80C186 Interface
Figure 44 shows the AD7933/AD7934 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent, high speed DMA channels where data transfers
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7933/AD7934 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation, which also resets the interrupt latch. Sufficient
priority must be assigned to the DMA channel to ensure that
the DMA request is serviced before the completion of the next
conversion.
*ADDITIONAL PINS OMITTED FOR CLARITY.
DMD0 TO DMD15
TMS320C50*
TMS320C25/
TMS32020/
80C186*
AD0 TO AD15
A16 TO A19
Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x
A0 TO A15
DRQ1
READY
ALE
WR
STRB
RD
MSC
INT
R/W
IS
X
ADDRESS/DATA BUS
Figure 44. Interfacing to the 80C186
DECODER
ADDRESS
ADDRESS
Q R
EN
ADDRESS BUS
LATCH
S
ADDRESS
DECODER
ADDRESS BUS
DATA BUS
TMS320C25
ONLY
DATA BUS
DSP/USER SYSTEM
CS
WR
RD
BUSY
DB11 TO DB0
MICROPROCESSOR/
CS
BUSY
RD
WR
DB0 TO DB11
AD7933/
AD7934*
USER SYSTEM
CONVST
AD7933/
AD7934*
CONVST