PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 14

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

1
6
3
4
7
9
11
13
14
15
16
17
18
19
5
8
10
12
20
21
28
1.3
Pin No.
P-LCC
Semiconductor Group
Pin Definitions and Functions
Symbol
V
INT
SP
IN1
IN5
IN9
IN13
IN14
IN15
IN10
IN11
IN6
IN7
IN2
IN0/TSC0
IN4/TSC1
IN8/TSC2
IN12/TSC3
IN3/DCL
A0
A1
SS
Input (I)
Output (O)
I
OD
open drain
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I
I
PCM-Input Ports: Serial data is received at these
lines at standard TTL levels.
Function
Ground (0 V)
Interrupt Request: The signal is activated when a
conference overflow is detected. The microproces-
sor may determine the specific conference in over-
flow by reading the conference status register
(CST). The interrupt is maskable. INT is an open
drain output, thus a ‘wired-or’ combination of inter-
rupt request outputs of several MUSAC-As is pos-
sible (a pull up resistor is necessary).
Synchronization Pulse: The MUSAC-A is syn-
chronized relative to the PCM system via this line.
PCM-Input Port / Tristate Control: In standard
configuration these pins are used as input lines, in
primary access configuration they supply control
signals for external devices.
PCM-Input Port / Data Clock: In standard config-
uration IN3 is the PCM-input line 3, in primary
access configuration it provides a 2048-kHz data
clock for the synchronous interface.
Address for Direct Register Access:
These pins are only active if a demultiplexed
If A1 is not connected it will be set to ground inter-
nally.
P-interface mode is selected.
14
PEB 2445
Overview
02.96