PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 35

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Latch Enable (ALE), the Interrupt (INT) and the Chip Select (CS) signal, as shown in
figure 16.
microprocessors. It gives access to the internal registers and to the control memories
(Connection Memory, Conference Control Memory).
Table 4
ALE
Fixed to ground
Switching
ALE is internally set to ground if it is not connected.
For a demultiplexed P interface the address bits A1 and A0 are needed for addressing
a register. For the P-interface timing please refer to chapter 5.3.
2.2
The MUSAC-A is programmed via the P interface. It consists of the address data bus
AD7
Figure 16
The MUSAC
The standard 8-bit P interface can communicate with Intel multiplexed/demultiplexed
Semiconductor Group
P-Interface Functions
AD0, the address bits A1
Microprocessor Interface and Registers
TM
-A Controlled by a Microprocessor
Type of
Intel
Intel
P Interface
A0, the Write (WR), the Read (RD), the Address
Bus Structure
demultiplexed
multiplexed
35
Pin 24
RD
RD
Functional Description
WR
WR
Pin 25
PEB 2445
02.96