PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 30

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

In primary access configuration the even output lines are affected by the XS2, XS1, XS0
and XFE entries in the clock shift register. The output frame is synchronized with the
rising edge of the SP signal.
Assuming a CSR entry X0
Programming the XS2, XS1 and XS0 bits with a value deviating from binary 000 the
output frame is delayed by 8
(XXXX0010) delays the output frame by 7-bit periods relative to the rising SP-pulse
edge.
Programming CSR:(XXXXXXX1) the output frame is delayed by another half a device
clock period. In figure 13 the outputting instants are shown for a device clock of 4096
and 8192 kHz and a CSR:(XXXX0001).
The last line in figure 13 shows an even 8192-kbit/s output line for the CSR entry
(XXXX1101) and an 8192-kHz device clock. The output frame is delayed by 2 1/2-bit
periods. For further examples refer to figure 20.
Figure 13 shows when the single bits are output. In standard configuration they are
clocked off at the rising clock edge at the beginning of the considered bit period.
Time-slot 0 starts two
Semiconductor Group
t
CP8
before the falling edge of the SP pulse.
H
the output frame starts with the rising edge of the SP pulse.
D
– (XS2, XS1, XS0)
30
B
bit periods. E.g, a CSR entry of
Functional Description
PEB 2445
02.96