PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet - Page 54

• Manufacturer Part Number: PEB2445NV1.2
• Manufacturer: Lantiq

Specifications of PEB2445NV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.6.2
Access: Read or write at address FF
Reset value: 00
RS2
RRE
XS0
XFE
Data stream manipulation according to these register entries only affects the system
interface and only in the primary access configuration. The frame structure can be
moved relative to the SP slope by up to 7 clock periods in half clock period steps. This
register can hold non-zero values only for a CFR:CFS value of logical 0.
Identical non-zero entries for RS2 – RS0 and XS2 – XS0 as well as identical RRE and
XFE generate an output time-slot structure which is 1 time-slot late relative to the input
time-slot structure.
Identical 000 entries for RS2 – RS0 and XS2 – XS0 as well as RRE and XFE being
logical 0 cause the input and output frames to coincide in time.
Semiconductor Group
XS2
RS0
Clock Shift Register (CSR)
AD7
RS2
H
Receive clock Shift, bits 2 – 0. The received data stream is shifted in bit
period steps.
Receive with Rising Edge. The data is sampled with the falling
(RRE = 0) or rising edge (RRE = 1) of the data equivalent clock.
Transmit clock Shift, bits 2 – 0. The transmitted data stream is shifted.
Transmit with Falling Edge; data is transmitted with the rising
(XFE = 0) or falling edge (XFE = 1) of the device clock.
RS1
RS0
H
RRE
54
XS2
XS1
Detailed Register Description
XS0
AD0
XFE
PEB 2445
02.96