PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 141

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Figure 49
The GHDLC unit and DSP always read and write to different areas in the RAM. Memory
is equally allocated to each of the receive and transmit buffer blocks (32 bytes each).
The DSP always writes to the block addresses. The switching between blocks is done
internally and does not concern the DSP.
4.7.5
Full Interrupt: A full interrupt is generated if:
• The receive buffer is full. The interrupt is issued immediately after the buffer has
• An end of a frame indication was detected at the beginning of a frame. The frame is
Empty Interrupt: An empty interrupt is generated every time a transmit buffer was
emptied by the GHDLC.
Note: Messages with zero byte data content are not supported.
4.7.6
4.7.6.1
The initialization procedure include writing for each HDLC it’s configuration to the
registers set. The four HDLCs will be arranged according to the specified configuration.
Data Sheet
become full.
programmable to 62.5 µs or 10 µs
of a buffer full indication followed by an end of frame indication, this condition
becomes only true if additionally there was no FULL interrupt during the previous
frame.
Transmit Buffer
Receive Buffer
GHDLC Interrupts
Operational Description
GHDLC Initialization
GHDLC Receive and Transmit Buffer Structure
DSP write
DSP read
(Chapter
Block
Block
Block
Block
124
6.2.6.15). To avoid a loss of data in case
GHDLC receive
GHDLC transmit
Functional Description
PEB 20570
PEB 20571
2003-07-31