PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 187

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

BBC(1:0)
AAC(1:0)
PLLINT
TX_EN
LOOP
PDOWN
Data Sheet
...
111 =
Balancing Bit Control (U
00 =
10 =
11 =
Adaptive Amplifier Control (S/T, U
00 =
10 =
11 =
Receive PLL Integrator (U
0 =
1 =
Transmitter Enable (S/T, U
0 =
1 =
Loop-back Mode in VIP Enable (S/T, U
0 =
1 =
Power Down Mode (S/T, U
16
Adaptive generation of balancing bit (depending on line delay).
upon reception of INFO3 or INFO4
Balancing bit control is disabled, and no balancing bit is added
Balancing bit control is disabled, and balancing bit is added
after each code violation in the M-bit (INFO3 or INFO4)
Adaptive amplifier control in VIP is enabled. The amplifier and
the equalizer are switched on/off depending on the level of the
received line signal with respect to the comparator threshold.
Adaptive amplifier control is disabled. The amplifier and the
equalizer are switched off permanently.
equalizer are switched on permanently
Programmable deviation disabled
Programmable deviation enabled, i.e., the RxPLL reacts only
after a certain number of consequent deviations from the PLL
controlling range.
Transmitter (analog line driver) is disabled (e.g. for non-
transparent analog loops in LT-T)
Transmitter is enabled (e.g. for switching of transparent analog
loops in LT-S)
Loops disabled
Loop-back enabled. Channel_m transmit data is looped back
to the receive data path (either transparent or non-transparent
according to state of bit TX_EN). Depending on bit EXLP the
loop is closed internally or externally.
Note: For U
Adaptive amplifier control is disabled. The amplifier and the
enable the test loop in the DELIC (n= IOM-2000 channel
number)
PN
PN
additionally bit TUTLR:UTn has to be set to
170
PN
)
PN
PN
)
)
)
PN
)
PN
)
Register Description
PEB 20570
PEB 20571
2003-07-31