PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 56

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 19
LTSC
(60)
TSC1
(79)
TSC0
(77)
Note: When the strap pins are not driven externally during reset, they are driven by
Note: Because of the internal pull-ups are too weak its recommended to connect any pin
Data Sheet
internal pull-ups/pull-downs. To reduce power consumption, the internal pull-up/
pull-down resistors are connected only during activated RESET input.
To ensure the default value of the straps, the pins must not be driven during reset.
In case of fixed external pull-up/pull-down, a pull-up/pull-down resistance of
10 K +/-10% is recommended.
used as a strap during reset, to an external pull-up/ pull-down resistor, even if it’s
supposed to be driven to it’s default strap-value.
PLL
BYPASS
PLL POWER
DOWN
RESET
COUNTER
BYPASS
Strap Pins (Evaluated During Reset) (cont’d)
0:
1: (default)
0:
1:(default)
0:
1: (default)
DSP_CLK input pin (the DSP fall-back clock)
is used as source for the 61 MHz clock
division chain. (Only for testing).
The PLL output is used as the source for the
61 MHz clock division chain.
The PLL is powered-down. (for IDDQ tests)
The PLL is on.
The reset-counter is bypassed, thus the
internal reset is the filtered reset. The internal
reset lasts 1-2 16 MHz cycles after a
deactivation of RESET.
The internal reset lasts 4-5 8 kHz cycles (>
500 s) after a deactivation of RESET
39
Pin Description
PEB 20570
PEB 20571
2003-07-31