PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 46

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 13
Pin
No.
12
13
14
15
7
6
5
Data Sheet
Symbol
CS
WR/
R/W
RD/
DS
ALE
MODE
IREQ
IACK
Microprocessor Bus Interface Pins (DELIC-PB) (cont’d)
Out (O)
I
I
I
I
I
O
(OD)
I
In (I)
During
Reset
I
I
I
I
I
High Z
(OD)
I
After
Reset
I
I
I
I
I
High Z
(OD)
I
29
Function
Chip Select
A "low" on this line selects all registers
for read/write operations.
Write (Intel/Infineon Mode)
Indicates a write access.
Read/Write (Motorola Mode)
Indicates the direction of the data
transfer
Read (Intel/Infineon Mode)
Indicates a read access.
Data Strobe (Motorola Mode)
During a read cycle, DS indicates that
the DELIC should place valid data on
the bus. During a write access, DS
indicates that valid data is on the bus.
Address Latch Enable
Controls the on-chip address latch in
multiplexed bus mode. While ALE is
’high’, the latch is transparent. The
falling edge latches the current
address. ALE is also evaluated to
determine the bus mode
(’low’=multiplexed,
’high’=demultiplexed)
Bus Mode Selection
Selects the µP bus mode
(’low’=Intel/Infineon, ’high’=Motorola)
Interrupt Request is programmable to
push/pull (active high or low) or open-
drain. This signal is activated when the
DELIC requests a µP interrupt. When
operated in open drain mode, multiple
interrupt sources may be connected.
Interrupt Acknowledge
Pin Description
PEB 20570
PEB 20571
2003-07-31