MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 48

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MCC501RX200TD0B

Manufacturer Part Number
MCC501RX200TD0B
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MCC501RX200TD0B

Package Type
BGA
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
MCC501RX200TD0B
Manufacturer:
FREESCALE
Quantity:
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48
Table 23 BMU SDRAM Interface Signals (continued)
C5NP
SIGNAL NAME
MA0 - MA11
MBA0 - MBA1
MCLK
MCASX
MRASX
MWEX
MCSX
MDQM
MDQML
CHAPTER 2: SIGNAL DESCRIPTIONS
PIN #
H22, I22, H23, H24, I24, H25, H26,
I26, H27, H28, I28, H29
G18, H19
I16
J21
I20
J20
H20
H21
G14
TOTAL
12
2
1
1
1
1
1
1
1
TYPE
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
O
O
nc
O
O
O
O
O
O
SIGNAL DESCRIPTION
Address Outputs: A0-A11 are sampled during the
ACTIVE command and READ/WRITE to select one
location out of the memory array in the respective
bank. The address inputs also provide the
op-code during a LOAD MODE REGISTER
command
Bank Address Outputs: BA0 and BA1 define which
bank the ACTIVE, READ, WRITE or PRECHARGE
command is being applied
Reserved
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered.
NOTE:
code.
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
Command Outputs: MRASX, MCASX, MWEX and
MCSX define the command being entered. MCSX
is considered part of the command code.
Chip Select: MCSX enables (registered LOW) and
disables (registered HIGH) the command decoder.
All commands are masked when MCSX is
registered HIGH. MCSX provides the external bank
selection on systems with multiple banks. MCSX is
considered part of the command code.
Input/Output Mask: MDQM is an input mask
signal for write accesses and an output enable
signal for read accesses. Input data is masked
when MDQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a high Z
state (two-clock latency) when MDQM is sampled
HIGH during the READ cycle.
NOTE: MDQML is an identical copy of MDQM
used to drive the loading on SDRAM
configurations with 2 DQM pins.
MCSX is considered part of the command

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