EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 71

• Manufacturer Part Number: EMC6D102-CZC-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of EMC6D102-CZC-TR

• Operating Current: 3mA
• Operating Temperature Classification: Commercial
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6]
7.2.31
7.2.32
Register
Address
Register
Address
82h
81h
Read/
Write
R/W
Read/
Write
R/W
See
Register 81h: TACH_PWM Association Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan
logic to determine when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
d. if the current value in Current PWM Duty registers is 00h or
e. if the fan is disabled via the Fan Configuration Register.
Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Tach4. These bits determine the PWM associated with this Tach. See bit combinations below.
Notes:
Register 82h: Interrupt Enable 3 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual thermal error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP),
Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
All TACH inputs must be associated with a PWM output. If the tach is not being driven by the
associated PWM output it should be configured to operate in Mode 1 and the associated TACH
interrupt must be disabled.
Figure 5.1 Interrupt Control on page
Interrupt Enable 3 (Temp)
TACH_PWM Association
00
01
10
11
Register Name
Register
Name
DATASHEET
(MSb)
Bit 7
RES
(MSb)
Bit 7
T4H
22.
71
Bit 6
RES
PWM Associated With Tachx
Bit 6
T4L
Bit 5
RES
Bit 5
T3H
Bit 4
RES
Bit 4
T3L
D2EN
Bit 3
Bit 3
T2H
Reserved
PWM1
PWM2
PWM3
D1EN
Bit 2
Bit 2
T2L
Bit 1
AMB
Bit 1
T1H
Revision 0.4 (09-25-07)
TEMP
(LSb)
(LSb)
Bit 0
Bit 0
T1L
Default
Default
Value
Value
A4h
0Eh