EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 79

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EMC6D102-CZC-TR

Manufacturer Part Number
EMC6D102-CZC-TR
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of EMC6D102-CZC-TR

Operating Current
3mA
Operating Temperature Classification
Commercial
Package Type
SSOP
Lead Free Status / Rohs Status
Compliant
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
Note 8.1
Note 8.2
Note 8.3
Note 8.4
Note 8.5
Note 8.6
The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / QJA.
Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V
for a rising edge. TRI-STATE output voltage is forced to 1.4V.
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Total Monitoring Cycle Time for cycle mode includes a one second delay plus all
temperature conversions and all analog input voltage conversions.
See
averaging options. Only the nominal default case is shown in this section.
All leakage currents are measured with all pins in high impedance.
The low output level for PWM pins is actually +8.0mA.
The h/w monitor analog block implements a 10-bit ADC. The output of this ADC goes to
an averager block, which can be configured to accumulate the averaged value of the
analog inputs. The amount of averaging is programmable. The output of the averaging
block produces a 12-bit temperature or voltage reading value. The 8 MSbits go to the
reading register and the 4 LSbits to the A/D LSb register.
Table 5.2, “Conversion Cycle Timing,” on page 19
DATASHEET
79
for conversion cycle timing for all
Revision 0.4 (09-25-07)

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