AD9726BSVZ Analog Devices Inc, AD9726BSVZ Datasheet - Page 2

• Manufacturer Part Number: AD9726BSVZ
• Description: IC DAC 16IT LVDS 400MSPS 80-TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9726BSVZ

• Data Interface: Parallel
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 575mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 400MSPS
• Input Channel Type: Parallel
• Supply Current: 80mA
• Digital Ic Case Style: QFP
• No. Of Pins: 80
• Package: 80TQFP EP
• Resolution: 16 Bit
• Conversion Rate: 400 MSPS
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: 0.003(Typ) %FSR
• Integral Nonlinearity Error: ±2.5 LSB
• Maximum Settling Time: 0.0105(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9726-EBZ - BOARD EVAL FOR AD9726
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9726
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 8
Pin Configuration and Function Descriptions ............................. 9
Terminology .................................................................................... 11
REVISION HISTORY
2/10—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 5
Added Figure 4 and Figure 5, Renumbered Sequentially ........... 6
Changes to Figure 5 and Table 7 ..................................................... 9
Changes to Table 9 .......................................................................... 16
Added Data Synchronization Circuitry Bypass Section ............ 18
Changes to Ordering Guide .......................................................... 24
DC Specifications ......................................................................... 3
AC Specifications .......................................................................... 4
Digital Signal Specifications ........................................................ 5
Timing Specifications .................................................................. 5
Timing Diagrams .......................................................................... 6
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Rev. B | Page 2 of 24
Typical Performance Characteristics ........................................... 12
Serial Port Interface ........................................................................ 15
Theory of Operation ...................................................................... 17
Outline Dimensions ....................................................................... 24
11/05—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Table 3 and Table 4 ....................................................... 5
Changes to the Terminology Section ........................................... 10
Changes to the Driving the DAC Clock Inputs Section ............ 15
Changes to the Reset and Serial Port Interface Sections ........... 17
Updated Outline Dimensions ....................................................... 22
Changes to the Ordering Guide ................................................... 22
7/05—Revision 0: Initial Version
DAC Clock and Data Clock Output ........................................ 17
Data Clock Input ........................................................................ 17
Data Synchronization Circuitry ............................................... 18
Analog Output ............................................................................ 18
Internal Reference and Full-Scale Output .............................. 19
Reset ............................................................................................. 19
Serial Port Interface ................................................................... 19
SPI Pin Description .................................................................... 20
Calibration ................................................................................... 20
Sync Logic Operation and Programming ............................... 22
Ordering Guide .......................................................................... 24