AD9726BSVZ Analog Devices Inc, AD9726BSVZ Datasheet - Page 6

• Manufacturer Part Number: AD9726BSVZ
• Description: IC DAC 16IT LVDS 400MSPS 80-TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9726BSVZ

• Data Interface: Parallel
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 575mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 400MSPS
• Input Channel Type: Parallel
• Supply Current: 80mA
• Digital Ic Case Style: QFP
• No. Of Pins: 80
• Package: 80TQFP EP
• Resolution: 16 Bit
• Conversion Rate: 400 MSPS
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: 0.003(Typ) %FSR
• Integral Nonlinearity Error: ±2.5 LSB
• Maximum Settling Time: 0.0105(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9726-EBZ - BOARD EVAL FOR AD9726
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9726
Parameter
SERIAL PORT INTERFACE
RESET PULSE WIDTH
TIMING DIAGRAMS
SCLK Frequency (f
SCLK Rise/Fall Time
SCLK Pulse Width High (t
SCLK Pulse Width Low (t
SCLK Setup Time (t
SDIO Setup Time (t
SDIO Hold Time (t
SDIO/SDO Valid Time (t
DH
SCLK
CSU
DSU
)
)
)
)
DV
CPWL
CPWH
)
)
)
DATACLOCK OUTPUT
DATACLOCK OUTPUT
DATACLOCK INPUT
DATACLOCK INPUT
IOUTA OR IOUTB
DAC CLOCK
DB0 TO DB15
DAC CLOCK
DATA BUS
DATA BUS
CLK+/CLK–
Figure 4. Data Synchronization Bypass Timing Diagram
Figure 2. DDR Timing Diagram
Figure 3. SDR Timing Diagram
Rev. B | Page 6 of 24
t
DSU-BYPASS
t
t
DCPD-DDR
DCPD-SDR
t
DSU-DDR
t
DSU-SDR
t
PD-BYPASS
Min
t
1.5
30
30
30
30
DH-BYPASS
0
t
t
DH-DDR
DH-SDR
Typ
Max
15
30
1
Unit
MHz
ms
ns
ns
ns
ns
ns
ns
ns