BOXDP965LTCK Intel, BOXDP965LTCK Datasheet - Page 55

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BOXDP965LTCK

Manufacturer Part Number
BOXDP965LTCK
Description
Manufacturer
Intel
Datasheet

Specifications of BOXDP965LTCK

Lead Free Status / Rohs Status
Compliant
2.7.2.1
Table 21. Chassis Intrusion Header
Table 22. Front and Rear Chassis Fan Headers
Table 23. Processor and Auxiliary Rear
The board has the following add-in card connectors:
Note the following considerations for the PCI Conventional bus connectors:
Pin
1
2
Pin
1
2
3
Pin
1
2
3
4
PCI Express x16: one connector supporting simultaneous transfer speeds up to
4 GBytes/sec of peak bandwidth per direction and up to 8 GBytes/sec concurrent
bandwidth
PCI Express x1: three PCI Express x1 connectors. The x1 interface supports
simultaneous transfer speeds up to 250 Mbytes/sec of peak bandwidth per
direction and up to 500 MBytes/sec concurrent bandwidth
PCI Conventional (rev 2.3 compliant) bus: three PCI Conventional bus add-in card
connectors. The SMBus is routed to PCI Conventional bus connector 2 only. PCI
Conventional bus add-in cards with SMBus support can access sensor data and
other information residing on the board.
All of the PCI Conventional bus connectors are bus master capable.
SMBus signals are routed to PCI Conventional bus connector 2. This enables PCI
Conventional bus add-in boards with SMBus support to access sensor data on the
board. The specific SMBus signals are as follows:
⎯ The SMBus clock line is connected to pin A40.
⎯ The SMBus data line is connected to pin A41.
Add-in Card Connectors
Chassis Fan Headers
Signal Name
Intruder
Ground
Signal Name
Control
+12 V
Tach
Signal Name
Ground
+12 V
FAN_TACH
FAN_CONTROL
Technical Reference
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