BOXDP965LTCK Intel, BOXDP965LTCK Datasheet - Page 79

• Manufacturer Part Number: BOXDP965LTCK
• Manufacturer: Intel

Specifications of BOXDP965LTCK

• Lead Free Status / Rohs Status: Compliant

Table 42. Port 80h POST Codes
POST Code
53 – 57
5A
5B
5C
5D
7A
10
11
12
13
21
22
23
24
25
26
27
28
50
51
52
58
59
70
71
72
78
79
Description of POST Operation
Power-on initialization of the host processor (Boot Strap Processor)
Host processor Cache initialization (including APs)
Starting Application processor initialization
SMM initialization
Initializing a chipset component
Reading SPD from memory DIMMs
Detecting presence of memory DIMMs
Programming timing parameters in the memory controller and the DIMMs
Configuring memory
Optimizing memory settings
Initializing memory, such as ECC init
Testing memory
Enumerating PCI busses
Allocating resources to PCI bus
Hot Plug PCI controller initialization
Reserved for PCI Bus
Resetting USB bus
Reserved for USB
Resetting PATA/SATA bus and all devices
Reserved for ATA
Resetting SMBUS
Reserved for SMBUS
Resetting the VGA controller
Disabling the VGA controller
Enabling the VGA controller
Resetting the console controller
Disabling the console controller
Enabling the console controller
ATA/ATAPI/SATA
Remote Console
Host Processor
Local Console
Memory
PCI Bus
Chipset
SMBus
USB
Error Messages and Beep Codes
continued
79