SCD240110QCM Intel, SCD240110QCM Datasheet - Page 104

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
8.2.5
104
Register Name: COR4
Register Description: Modem Change Options and FIFO Transfer Threshold
Default Value: x’00
Access: Byte Read/Write
DSRzd
Bit 7
Bit 5
Bit 4
Bits 3:0
Channel Option Register 4 (COR4)
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:0
CDzd
Bit 6
There is no character synchronization in certain phases of X.21 call setup. When a
data change occurs in a non-character synchronous phase, a partial character can be
detected before the steady state is detected or character sync is achieved. In these
conditions, the partial character is passed to the host as normal data.
Strip SYN
When this bit is set, SYN characters are treated as special receive conditions; when
two SYN characters are received, a special character interrupt is generated (see
RISR) and following SYN characters are stripped from the incoming datastream. If
this bit is not set, the SYN characters are treated as normal data and passed to the
host in Good Data interrupts; they are still used to obtain character synchronization
with the data.
Special Character Detect Enable
SCDE is only available when SSDE mode (see above) is enabled. If enabled, the
characters programmed in SCHR1–3 are treated as the steady-state conditions in
SSDE mode. They are validated for two character times, a special character interrupt
is generated and subsequent repetitions of the same data pattern are filtered from the
datastream.
Reserved – must be ‘0’; reads back as ‘0’.
Detect one-to-zero transition on DSR*
1 = detect one-to-zero transition on the DSR* input (zero-to-one transition on
MSVR[7]).
Detect one-to-zero transition on CD*
1 = detect one-to-zero transition on the CD* input (zero-to-one transition on
MSVR[6]).
Detect one-to-zero transition on CTS*
1 = detect one-to-zero transition on the CTS* input (zero-to-one transition on
MSVR[5]).
Reserved – must be ‘0’.
FIFO threshold in characters
Note that the maximum value allowable for this field is 12 (0C hex). These 4 bits
(binary-encoded field) set the FIFO transfer threshold for both transmit and receive
FIFOs, in both Interrupt and DMA Transfer modes.
CTSzd
Bit 5
Bit 4
0
Bit 3
Bit 2
FIFO Threshold
Motorola Hex Address: x’15
Bit 1
Intel Hex Address: x’16
Datasheet
Bit 0