SCD240110QCM Intel, SCD240110QCM Datasheet - Page 94
SCD240110QCM
Manufacturer Part Number
SCD240110QCM
Description
Manufacturer
Intel
Datasheet
1.SCD240110QCM.pdf
(176 pages)
Specifications of SCD240110QCM
Operating Supply Voltage (max)
7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / Rohs Status
Not Compliant
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CD2401 — Multi-Protocol Communications Controller
8.2.2
94
Register Name: COR1
Register Description: Channel Option 1
Default Value: x’00
Access: Byte Read/Write
AFLO
Bit 7
Channel Option Register 1 (COR1)
COR1 — HDLC Mode
An Initialization command must be given to CD2401 through the CCR if any options specified in
this register are changed.
Bit 7
Bit 6
Bits 5:4
Bits 3:0
ClrDet
Bit 6
Address Field Length Option
0 = address field is one octet in length
1 = address field is two octets in length
Clear Detect for X.21 data transfer phase
0 = clear detect disabled
1 = clear detect enabled
A clear is defined as two consecutive all zeros receive characters, with the CTS* pin
high.
Addressing modes [1:0]
00 = no address recognition
01 = 4
10 = 2
If this bit is set, RFARs should contain the address to be matched. If AFLO
(COR1[7]) is set to ‘1’, an address match is made against the RFAR1 and RFAR2
pair, or the RFAR3 and RFAR4 pair.
Inter-frame flag option [3:0]
These bits define the minimum number of flags transmitted before a frame is started.
The minimum number of opening flags always precede a frame when idle in mark
is set, or always separates two consecutively transmitted frames. No restriction is
placed on the number of flags between received frames.
AdMde1
Bit 5
Flag3
0
0
1
1 byte
2 byte.
Flag2
AdMde0
0
0
1
Bit 4
through
Flag1
0
0
1
Flag3
Bit 3
Flag0
0
1
1
Minimum of one opening flag, with shared
closing/opening flags permitted.
Minimum number of opening flags sent.
Flag2
Bit 2
Function
Motorola Hex Address: x’10
Flag1
Bit 1
Intel Hex Address: x’13
Datasheet
Flag0
Bit 0
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