SCD240110QCM Intel, SCD240110QCM Datasheet - Page 79

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

6.3
6.3.1
6.3.2
Datasheet
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Bisync Processing
In both transmit and receive, the CD2401 interprets the first characters of data to determine the
type of frame and compile the corresponding BCC. The host uses COR1 to program parity options
and character length, and COR2 to program the character set (ASCII or EBCDIC) and determine
whether to use CRC-16 or LRC.
Bisync Transmit Processing
The CD2401 can be programmed to idle in either SYN or mark. When idling in mark, a
programmable number of leading pad characters can be transmitted before each data frame. The
leading pads ensure the remote phase-locked loop has sufficient transitions to achieve bit
synchronization before data starts. The leading pad character can be programmed as AA (suitable
for NRZ and Manchester) or 00 (suitable for NRZI).
When data is available in the FIFO, transmission starts; any required leading pads are sent,
followed by a SYN pair and the CPU-supplied data. The CD2401 monitors the transmit data to
determine frame type and compute the correct BCC, thus eliminating unnecessary characters from
the calculation. If SYN sequences are embedded in the data supplied by the CPU, they are
transmitted — but excluded — from the BCC calculation.
If a frame transmission is aborted by the STCR, an EOT and a trailing pad are transmitted and the
line returned to its idle state. A frame is terminated normally when an EOF indication is passed to
the CD2401, either in TEOIR or in A/BTBSTS. If the frame ends with an EOT or ENQ condition,
the trailing pad is appended and transmission is complete; otherwise, any accumulated BCC is
appended followed by the trailing pad, and the line returns to the idle state.
Bisync Receive Processing
After initialization, the receiver starts in Synchronous Hunt mode and discards data until a pair of
SYN characters are detected. The next non-SYN data is assumed to be the start of frame. The
receive data is continuously monitored to determine the type of frame (transparent/non-transparent,
BCC/no BCC). If required, the BCC is compiled excluding any characters that should not be part
of the calculation. When a frame terminating condition is detected and if a BCC was accumulated,
it is checked and the EOF information is passed to the CPU by the RISRs. If the frame is
terminated with an ENQ condition, the BCC is not checked and an abort indication is passed to the
CPU by the RISRs.
An extra-frame-termination process is available by programming an extra-frame-termination
character into COR6. When this character is detected, the receive frame is terminated immediately
and no BCC is computed. Following an initialize channel command, COR6 is set to the value of
DLE (10 hex) by the internal code; the user can alter this to any other value. To detect the condition
where the frame termination character was corrupted on a non-transparent line, COR6 can be
programmed to the idle condition, FF hex. To use this on a transparent line, the data should not
equal FF; if the value in COR6 is preceded by the DLE character, it does not cause frame
termination.
Multi-Protocol Communications Controller — CD2401
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