SCD240110QCM Intel, SCD240110QCM Datasheet - Page 109

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

8.2.9
8.2.9.1
Datasheet
Register Name: SCHR1
Register Description: Special Character 1
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 5
Bits 4:2
Bits 1:0
Special Character Registers — Async Mode only
Special Character registers can be used for detecting specific receive characters in the incoming
datastream and can be used to transmit characters (by STCR) preempting any data in the transmit
FIFO.
Special Character Register 1 (SCHR1)
Bit 6
LNE provides a mechanism to transfer flow control and special characters as normal
data, without invoking flow control action in the CD2401 and without generating
special interrupts. The LNext character is defined in the LNXT register and, when
processed, is always passed to the host CPU as normal data.
Flow Control on Error characters
0 = characters received with an error are not processed for special character/flow
control matching.
1 = all receive characters, even those with errors, are processed for special character/
flow control processing.
Reserved – must be ‘0’.
Transmit processing for CR and NL; these bits define the Translation mode when CR
and/or NL are present in the transmit data.
Bit 5
ONLCR
0
0
1
1
User-Defined Special Character
OCRNL
Bit 4
XON Character
0
1
0
1
Multi-Protocol Communications Controller — CD2401
No special action.
CR translated to NL.
NL translated to the sequence CR NL.
CR translated to NL, and NL translated to the sequence
CR NL.
Bit 3
Bit 2
Function
Motorola Hex Address: x’1F
Bit 1
Intel Hex Address: x’1C
Bit 0
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