SCD240110QCM Intel, SCD240110QCM Datasheet - Page 134

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

CD2401 — Multi-Protocol Communications Controller
8.5.2.7
134
Register Name: REOIR
Register Description: Receive End of Interrupt
Default Value: x’00
Access: Byte Write only
TermBuff
Bit 7
This Virtual register accesses the receive data FIFO of a channel interrupting for receive data transfer. This
register address is used for all channels to transfer receive FIFO data to the host (if programmed in Interrupt
Transfer mode). Data must be read as bytes, and follows the conventions for the positioning of valid data on the
bus. If the BYTESWAP pin is high, data is valid on A/D[7:0]; if BYTESWAP is low, data is valid on A/D[15:8]. This
is true because the RDR is on an even address.
Receive End of Interrupt Register (REOIR)
This must be written to by the host receive interrupt service routine to signal to the CD2401 that the
current interrupt service is concluded. This must be the last access to the CD2401 during an
interrupt service routine. A write to this register generates an internal end-of-interrupt signal that
pops the CD2401 interrupt context stack.
Depending on the circumstances of an individual interrupt service, the host may be required to pass
a parameter to the CD2401 through these registers. The CD2401 interprets the values written to
this register at the completion of all receive interrupts as commands to be executed.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DiscExc
Bit 6
Terminate current DMA Buffer
If this bit is set, the current receive buffer is terminated and data transfer is switched
to the other buffer. This bit should only be set in response to an Async Exception
interrupt. If the buffer is terminated in response to an Exception Character (that is,
Parity Error) interrupt and the DiscExc bit is not set, the exception character is writ-
ten at the start of the next buffer.
Before writing the terminate buffer command to REOIR, a new buffer descriptor can
be written to the current buffer.
Discard Exception Character (DMA mode only)
When this bit is set in response to an Async Exception interrupt, the exception char-
acter is not transferred to memory.
Set General Timer 2 (Synchronous modes)
0 = do not set General Timer 2.
1 = load the value provided in RISRl to General Timer 2.
Set General Timer 1 (Synchronous modes)
0 = do not set General Timer 1.
1 = load the value provided in RISRl to the high byte of General Timer 1.
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in RISR. When the timer reaches zero, the CD2401 generates a modem/timer
group interrupt to the host.
No Transfer of Data
If no data is transferred from the receive FIFO during a receive interrupt, this bit
must be set by the host.
SetTm2
Bit 5
SetTm1
Bit 4
NoTrans
Bit 3
Gap2
Bit 2
Motorola Hex Address: x’84
Gap1
Bit 1
Intel Hex Address: x’87
Datasheet
Gap0
Bit 0