SCD240110QCM Intel, SCD240110QCM Datasheet - Page 47

• Manufacturer Part Number: SCD240110QCM
• Manufacturer: Intel

Specifications of SCD240110QCM

• Operating Supply Voltage (max): 7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

5.4.4
Datasheet
Ntbuf
Table 3. A and B Buffers and Chaining
0
0
1
1
1
0
0
1
1
2401own
Buffer A
If there is a non-zero value in the BERCNT register, the register is decremented and the failed
transfer is retried automatically. If the BERCNT is zero, a bus error interrupt is generated and
DMA transfers are suspended on the failing buffer until the interrupt is serviced.
A and B Buffers and Chaining
The buffer management of the CD2401 uses a dual-buffer scheme. There is an A and B buffer pair
for each transmitter and each receiver. Each buffer is controlled by an Ownership Status bit, called
2401own. When 2401own is set to ‘1’, the CD2401 owns the buffer. When 2401own is set to ‘0’,
the host owns the buffer. A simple rule prevents confusion in the buffer management: neither the
CD2401 nor the host seizes buffer ownership. Each always relinquishes ownership to the other.
The host relinquishes ownership of a receive buffer to the CD2401 when the receive buffer is
ready. The CD2401 is then free to write received data into the buffer. The CD2401 returns
ownership of the receive buffer after the receive data is in the buffer. The host gives ownership of a
transmit buffer to the CD2401 when the transmit buffer is ready to transmit. The CD2401 then
transmits the contents of the buffer. When this is complete, the CD2401 returns ownership back to
the host.
The CD2401 keeps track of which buffer (A or B) is to be used next in the status bits — Ntbuf for
transmit and Nrbuf for receive. The relationship between the 2401own bit and the ‘next’ bits is
shown later. The receive buffers are handled in the same way using the Nrbuf (next receive buffer).
Chaining is used to break up relatively long frames into shorter blocks in memory, and is useful
where there are frequent smaller frames and occasional long frames. Chaining allows more
efficient use of the user RAM.
The EOF Status bit controls chaining in Synchronous modes. Chaining applies to both transmit and
receive. For transmit, the host determines EOF bit; for receive, the CD2401 determines the EOF
bit.
In Transmit DMA when the first buffer is supplied to the CD2401, it is treated as the start of frame
— the CRC is reset and leading pad/flag/syn characters are transmitted, followed by the data. If the
EOF bit is set, the CRC and closing flag/syn are appended, and the next buffer is again treated as
the start of frame. If the EOF bit is not set, the CD2401 treats the buffer as the first part of a larger
frame and chains into the next buffer (does not reset CRC); this process continues until a buffer is
supplied with the EOF bit set.
0
1
1
0
0
0
1
1
0
2401own
Buffer B
0
0
0
0
1
1
1
0
0
Send nothing.
Host sets up buffer A.
CD2401 accepts buffer A and marks B as next.
CD2401 completes A transfer, and passes it to host.
Host sets up buffer B.
CD2401 accepts B and marks A as next.
Host sets up buffer A.
CD2401 completes B transfer, passes to host, accepts A and marks B as next.
CD2401 completes A transfer and passes it to host.
Multi-Protocol Communications Controller — CD2401
Transmit Action
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