TC59SM808BFTL-70 Toshiba, TC59SM808BFTL-70 Datasheet - Page 3

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TC59SM808BFTL-70

Manufacturer Part Number
TC59SM808BFTL-70
Description
Manufacturer
Toshiba
Datasheet

Specifications of TC59SM808BFTL-70

Lead Free Status / Rohs Status
Not Compliant
BLOCK DIAGRAM
A11, A12
A0~A9
NOTE: The TC59SM804BFT/BFTL configuration is 8192 × 2048 × 4 of cell array with the DQ pins numbered DQ0~DQ3.
RAS
CKE
CAS
CLK
BS0
BS1
A10
WE
CS
The TC59SM808BFT/BFTL configuration is 8192 × 1024 × 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59SM816BFT/BFTL configuration is 8192 × 512 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
COUNTER
REFRESH
COMMAND
DECODER
ADDRESS
BUFFER
BUFFER
CLOCK
COUNTER
COLUMN
GENERATOR
REGISTER
CONTROL
SIGNAL
MODE
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
TC59SM816/08/04BFT/BFTL-70,-75,-80
CELL ARRAY
CELL ARRAY
DATA CONTROL
BANK #0
BANK #2
CIRCUIT
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
DQ BUFFER
BANK #1
BANK #3
2001-06-11 3/49
DQ0~DQn
DQM

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