TC59SM808BFTL-70 Toshiba, TC59SM808BFTL-70 Datasheet - Page 39

• Manufacturer Part Number: TC59SM808BFTL-70
• Manufacturer: Toshiba

Specifications of TC59SM808BFTL-70

• Lead Free Status / Rohs Status: Not Compliant

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read. The minimum values of CAS Latency depends on the frequency of CLK. The minimum value which
satisfies the following formula must be set in this field.
Test mode entry bit (A7)
Reserved bits (A8, A10, A11, A12, BS0, BS1)
Single Write mode (A9)
selected. When the A9 bit is 1, Burst Read and Single Write mode are selected.
CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data
This bit is used to enter Test mode and must be set to 0 for normal operation.
These bits are reserved for future operations. They must be set to 0 for normal operation.
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are
Read Cycle CAS Latency = 3
Addressing sequence example (Burst Length = 8 and input address is 13.)
DQ0~DQ7
Command
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
DATA
Address
Address
A6
A9
0
0
0
1
Data
Burst Read and Single Write
A8
Burst Read and Burst Write
0
0
0
0
0
0
0
0
Interleave mode
Sequential mode
Read
A7
A5
0
0
0
0
0
0
0
0
13
1
1
0
Write Mode
A6
0
0
0
0
0
0
0
0
1
A5
0
0
0
0
0
0
0
0
2
Interleave Mode
A4
0
0
0
0
0
0
0
0
A4
Q0
0
1
13
13
3
A3
TC59SM816/08/04BFT/BFTL-70,-75,-80
1
1
1
1
1
1
1
1
Q1
12
14
4
A2
1
1
1
1
0
0
0
0
Q2
15
CAS Latency
15
5
2 clock
3 clock
A1
0
0
1
1
0
0
1
1
Q3
14
6
8
A0
1
0
1
0
1
0
1
0
Q4
7
9
9
ADD
13
12
15
14
10
11
9
8
Q5
10
8
8
13 + 1
13 + 2
13 + 3
13 + 4
13 + 5
13 + 6
13 + 7
13
Q6
11
11
9
ADD
Sequential Mode
13
14
15
10
12
2001-06-11 39/49
11
8
9
Q7
10
10
12
calculated using
A2, A1 and A0 bits
not carry from
A2 to A3 bit.
11