K4H281638B-TCB0000 Samsung Semiconductor, K4H281638B-TCB0000 Datasheet - Page 25

• Manufacturer Part Number: K4H281638B-TCB0000
• Manufacturer: Samsung Semiconductor

Specifications of K4H281638B-TCB0000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

128Mb DDR SDRAM
3.3.5 Read Interrupted by a Precharge
for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS
latency.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge
time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be
satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by
the earliest possible Precharge command which does not interrupt the burst.
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same
bank before the Read burst is complete. The following functionality determines when a Precharge command
may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.
CAS Latency=2
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required
may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL
is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS
Precharge time).
the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where
CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new
Bank Activate command may be issued to the same bank after tRP.
bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the
Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal
precharge occurs at the same time as the earliest possible external Precharge command would initiate a
precharge operation without interrupting the Read burst as described in 1 above.
clock cycles between a Precharge command and a new Bank Activate command to the same bank equals
tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of
clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands
can only be given on a rising clock edge).
< Burst Length=8, CAS Latency=2 >
Command
CK
CK
DQS
DQ s
READ
Figure 13. Read interrupted by a precharge timing
0
1t
CK
Precharge
1
NOP
Dout 0 Dout 1 Dout 2 Dout 3
2
- 25 -
NOP
3
Interrupted by precharge
NOP
Dout 4 Dout 5 Dout 6 Dout 7
4
NOP
5
REV. 1.31 Nov. 3. 2001
NOP
6
NOP
7
NOP
8