LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 14

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
True Dual-Port SRAM Mode
In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent
read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the
MFB. Figure 9 shows the block diagram of the dual port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same
clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and
reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5
shows the possible sources for the clock, clock enable and initialization signals for the various registers.
Figure 9. Dual-Port SRAM Block Diagram
Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Register
RESET
Clock
Clock Enable
Reset
68 Inputs
CLK0
CLK1
CLK2
CLK3
Routing
From
Input
Read/Write Address
(ADA[0:8-12])
Clock A
PORT A
Reset A
Clk En A
Write/Read A
Chip Sel A
Write Data
(DIA[0:0,1,3,7,15])
PORT B
CSB[0,1], DIB[0:0,1,3,7,15]
CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected sig-
nal can be inverted if desired.
CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected sig-
nal can be inverted if required.
Created by the logical OR of the global reset signal and RSTA (RSTB).
RSTA (RSTB) can be inverted is desired.
ADB[0:8-12], RSTB,
Similar signals
CLKB, CENB, WRB,
as PORT A:
(RSTA)
(CLKA)
(CENA)
(CSA [0:1])
(WRA)
10
‘
‘
SRAM
Array
Dual
Port
ispXPLD 5000MX Family Data Sheet
Source
RD Data A
RD Data B
(DOA[0:0-15])
(DOB[0:0-15])