LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 38

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Lattice Semiconductor
t
t
t
t
t
t
Optional Adjusters
t
t
t
t
t
Input and Output Buffer Delays
t
t
FIFO
t
t
t
t
t
t
t
CASC
CICOMFB
CICOMC
FLAG
FLAGEXP
SUM
BLA
EXP
INDIO
PLL_SEC_DELAY
INEXP
IOI
IOO
FIFOWCLKS
FIFOWCLKH
FIFOCLKSKEW
FIFOFULL
FIFOAFULL
FIFOEMPTY
FIFOAEMPTY
Parameter
Additional Delay for
PT Cascading
between MFBs
Carry Chain Delay,
MFB to MFB
Carry Chain Delay,
Macro-Cell to
Macro-Cell
Routing Delay for
Extended Function
Flags
Additional Flag
Delay when
Expanding Data
Widths
Counter Sum Delay
Block Loading
Adder
PT Expander Adder
Additional Delay for
the Input Register
Secondary PLL
Output Delay
MFB Input Extender
Input Buffer Selec-
tion Adder
Output Buffer
Selection Adder
Write Data Setup
before Write Clock
Time
Write Data Hold
after Write Clock
Time
Opposite Clock
Cycle Delay
Write Clock to Full
Flag Delay
Write Clock to
Almost Full Flag
Delay
Read Clock to
Empty Flag Delay
Read Clock to
Almost Empty Flag
Delay
Description
Over Recommended Operating Conditions
t
t
t
t
FLAGAEMPTY
GCLK_IN,
Parameter
FLAGEMPTY
t
t
FLAGAFULL,
t
FLAGFULL
PLL_DELAY
GOE,
t
t
t
t
ROUTE
ROUTE
ROUTE
Base
t
INREG
t
PTSA
BUF
—
—
—
—
—
—
—
—
—
—
—
t
RST
t
IN,
,
,
-0.27
-0.01
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-4
0.71
0.35
0.10
2.62
2.57
0.80
0.04
0.53
0.50
0.91
0.62
1.40
3.08
3.08
3.08
3.08
—
—
34
-0.27
-0.01
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-45
Refer to sysIO Adjuster Tables
0.80
0.39
0.11
2.94
2.89
0.90
0.04
0.60
0.56
0.91
0.70
1.40
3.08
3.08
3.08
3.08
—
—
ispXPLD 5000MX Family Data Sheet
-0.22
-0.01
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
0.89
0.44
0.13
3.27
3.21
1.00
0.05
0.66
0.63
0.91
0.78
1.76
3.85
3.86
3.86
3.86
—
—
-0.22
-0.01
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-52
0.92
0.46
0.13
3.40
3.34
1.04
0.05
0.69
0.65
0.91
0.81
1.76
3.85
3.86
3.86
3.86
—
—
-0.21
-0.01
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-75
1.33
0.66
0.19
4.91
1.83
4.00
4.01
4.01
4.01
4.82
1.50
0.07
0.99
0.94
0.91
1.16
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns