LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 7

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LC5512MV-45FN484C

Manufacturer Part Number
LC5512MV-45FN484C
Description
CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
Manufacturer
Lattice
Datasheet

Specifications of LC5512MV-45FN484C

Package
484BGA
Family Name
ispXPLD™ 5000MV
Device System Gates
150000
Number Of Macro Cells
512
Maximum Propagation Delay Time
4.5 ns
Number Of User I/os
253
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
275 MHz
Number Of Product Terms Per Macro
160
Memory Type
EEPROM/SRAM
Ram Bits
262144
Operating Temperature
0 to 90 °C

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC5512MV-45FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing
Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance
access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs
are provided to allow the synthesis of new clocks and control of clock skews.
Multi-Function Block (MFB)
Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides
a flexible approach to implementing logic and memory that allows the designer to achieve the mix of functions that
are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are:
The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multi-
function array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs
data along with certain control functions to the macrocells. Output signals can be routed internally for use else-
where in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various
configurations are described in more detail in the following sections.
Figure 2. MFB Block Diagram
• SuperWIDE Logic Mode
• True Dual-port SRAM Mode
• Pseudo Dual-port SRAM Mode
• Single-port SRAM Mode
• FIFO Mode
• Ternary CAM Mode
(68 Input * 164 Product
Multifunction Array
Term Array, 32 MC)
True Dual Port
Pseudo Dual
Ternary CAM
Single Port
(16,384 bit)
Port RAM
(16,384 bit)
(16,384 bit)
(8,192 bit)
(128*48)
FIFO
Logic
RAM
RAM
Cascade Out
3
To Routing
ispXPLD 5000MX Family Data Sheet
Sharing
PTOE

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