LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 5

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

February 2010
Features
 Flexible Multi-Function Block (MFB)
 sysCLOCK™ PLL Timing Control
 sysIO™ Interfaces
Table 1. ispXPLD 5000MX Family Selection Guide
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Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
t
t
t
f
Functional Gates
I/Os
Packages
PD
S
CO
MAX
(Register Set-up Time)
Architecture
(Propagation Delay)
(Register Clock to Out Time)
• SuperWIDE™ logic (up to 136 inputs)
• Arithmetic capability
• Single- or Dual-port SRAM
• FIFO
• Ternary CAM
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
• LVCMOS 1.8, 2.5, 3.3V
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• LVTTL
(Maximum Operating Frequency)
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
– Open drain operation
down, bus-keeper, or none)
ispXPLD 5256MX
256 fpBGA
300MHz
4.0ns
2.2ns
2.8ns
128K
48K
75K
256
141
8
2
eXpanded Programmable Logic Device XPLD™ Family
ispXPLD 5000MX Family
1
3.3V, 2.5V and 1.8V In-System Programmable
 Expanded In-System Programmability (ispXP™)
 High Speed Operation
 Low Power Consumption
 Easy System Integration
ispXPLD 5512MX
149/193/253
256 fpBGA
484 fpBGA
208 PQFP
275MHz
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
• Infinitely reconfigurable via IEEE 1532 or sys-
• Design security
• 4.0ns pin-to-pin delays, 300MHz f
• Deterministic timing
• Typical static power: 20 to 50mA (1.8V),
• 1.8V core for low dynamic power
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
4.5ns
2.8ns
3.0ns
256K
150K
96K
512
16
Interface
CONFIG™ microprocessor interface
30 to 60mA (2.5/3.3V)
(5000MC) power supply operation
interfaces
2
TM
ispXPLD 5768MX ispXPLD 51024MX
256 fpBGA
484 fpBGA
250MHz
193/317
5.0ns
2.8ns
3.2ns
225K
384K
144K
768
24
2
484 fpBGA
672 fpBGA
MAX
250MHz
317/381
1,024
3.0ns
512K
192K
5.2ns
3.7ns
300K
32
Data Sheet
2
5kmx_12.4