DSP56301AG80 Freescale Semiconductor, DSP56301AG80 Datasheet - Page 14

• Manufacturer Part Number: DSP56301AG80
• Description: IC DSP 24BIT 80MHZ GP 208-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56301AG80

• Interface: Host Interface, SSI, SCI
• Clock Rate: 80MHz
• Non-volatile Memory: ROM (9 kB)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
1.7 Host Interface (HI32)
The Host Interface (HI32) provides fast parallel data to a 32-bit port directly connected to the host bus. The HI32
supports a variety of standard buses and directly connects to a PCI bus and a number of industry-standard
microcomputers, microprocessors, DSPs, and DMA hardware.
1.7.1
Careful synchronization is required when the system reads multiple-bit registers that are written by another
asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the
Host port). The considerations for proper operation are discussed in Table 1-10.
1-10
MODD
IRQD
RESET
Asynchronous read of
receive byte registers
Asynchronous write to
transmit byte registers
Signal Name
Action
Host Port Usage Considerations
Input
Input
Input
Type
When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or
Receive register Low (RXL), use interrupts or poll the Receive register Data Full (RXDF) flag that indicates
data is available. This assures that the data in the receive byte registers is valid.
Do not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or
Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set, indicating that the
transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the
Host Receive (HRX) register.
Table 1-9.
Table 1-10.
Input
Input
State During
Reset
DSP56301 Technical Data, Rev. 10
Interrupt and Mode Control (Continued)
Host Port Usage Considerations
Mode Select D
Selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
IRQD during normal instruction processing. MODA, MODB, MODC, and
MODD select one of sixteen initial chip operating modes, latched into the OMR
when the RESET signal is deasserted.
External Interrupt Request D
Internally synchronized to CLKOUT. If IRQD is asserted synchronous to
CLKOUT, multiple processors can be re-synchronized using the WAIT
instruction and asserting IRQD to exit the Wait state. If the processor is in the
Stop stand-by state and IRQD is asserted, the processor exits the Stop state.
These inputs are 5 V tolerant.
Reset
Deassertion of RESET is internally synchronized to the clock out (CLKOUT).
When asserted, the chip is placed in the Reset state and the internal phase
generator is reset. The Schmitt-trigger input allows a slowly rising input (such
as a capacitor charging) to reset the chip reliably. If RESET is deasserted
synchronous to CLKOUT, exact start-up timing is guaranteed, allowing
multiple processors to start synchronously and operate together in “lock-step.”
When the RESET signal is deasserted, the initial chip operating mode is
latched from the MODA, MODB, MODC, and MODD inputs. The RESET
signal must be asserted after power-up.
This input is 5 V tolerant.
Description
Signal Description
Freescale Semiconductor