DSP56301AG80 Freescale Semiconductor, DSP56301AG80 Datasheet - Page 17

• Manufacturer Part Number: DSP56301AG80
• Description: IC DSP 24BIT 80MHZ GP 208-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56301AG80

• Interface: Host Interface, SSI, SCI
• Clock Rate: 80MHz
• Non-volatile Memory: ROM (9 kB)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
HPAR
HDAK
HPERR
HDRQ
HGNT
HAEN
HREQ
HTA
Signal Name
Input/
Output
Input
Input/
Output
Output
Input
Input
Output
Output
Type
Tri-stated
Tri-stated
Input
Tri-stated
State During
Table 1-11.
Reset
DSP56301 Technical Data, Rev. 10
Host Parity
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Parity signal.
Host DMA Acknowledge
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Host DMA Acknowledge Schmitt-trigger
signal.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Parity Error
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Parity Error signal.
Host DMA Request
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Host DMA Request output.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Bus Grant
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Bus Grant signal.
Host Address Enable
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Host Address Enable output signal.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Bus Request
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Bus Request signal.
Host Transfer Acknowledge—When HI32 is programmed to interface with a
universal, non-PCI bus and the HI function is selected, this is the Host Data
Bus Enable signal. HTA can be programmed as active high or active low.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
Host Interface (Continued)
Signal Description
Host Interface (HI32)
1-13